VHDL help in state machines!!

[TrickyDicky]

yes. If you get a special byte you can just force a reset. somthing like this:

count_proc : process(reset, clk)
begin
  if reset = '1' then
    count <= 0;
  elsif rising_edge(clk) then
    if input = speicial_byte then
      count <= 0;
    else
      count <= next_count;
    end if;
  end if;
end process;

I think you really need to think about how your circuit is working. Have a go at drawing out your circuit on paper before writing VHDL.

 

[ellis91]

@trickydicky:
Thanks a lot. I tried adding the reset, but realised i was adding another complication. i thought i could without adding it.
I'm posting the modified code, but i'm experiencing another challenge..



This is the modified code.

entity final_packet_format_error_detection is
port (

data_receive: in STD_LOGIC_VECTOR(0 to 7);

clock : in STD_LOGIC;

special_byte : in STD_LOGIC_VECTOR(0 to 7);
no_of_bytes: in integer range 0 to 1024;

no_error_bytes : inout integer range 0 to 1024 ;
no_special_bytes : inout integer range 0 to 1024 ;
byte_count : inout integer range 0 to 1024

);

end final_packet_format_error_detection;

architecture Behavioral of final_packet_format_error_detection is

type statetype is (START_DETECTION, ANALYZE_DATA);
signal state, next_state: statetype;


begin




operation: process(state, data_receive, special_byte, no_error_bytes, no_special_bytes, clock )
begin


if (clock'event and clock='1') then

case state is




when START_DETECTION => if(data_receive = special_byte) then
state <= ANALYZE_DATA;
else
state <= START_DETECTION;
byte_count <= byte_count + 1;
end if;


when ANALYZE_DATA =>

if(byte_count = no_of_bytes) then
no_special_bytes <= no_special_bytes + 1;
byte_count <= 0;
state <= START_DETECTION;
else
no_special_bytes <= no_special_bytes + 1;
no_error_bytes <= no_error_bytes + 1;
byte_count <= 0;
state <= START_DETECTION;
end if;


end case;

end if;
end process;
end Behavioral;

I want the state transitions to take place in one clock cycle. Presently, it changes state at each rising edge. The problem with this is that by the time it does into the analyze_data state, the data value of byte_count has already changed. Hence, it isn't doing the designated function.

 

[TrickyDicky]

this is where you have to start managing pipelining

But its already looking a lot better.

 

[ellis91]

it atleast is workin for a change.. is there any way i can have a single series of state transitions to happen in one clock cycle?..

 

[TrickyDicky]

I think think yiou're jumping too far ahead without understanding the digital logic fundamentals. You would never have more than one state transition in a signle clock cycle because you only change states based on various inputs when the clock rises (ie. 1 check per clock).

Have you tried working this circuit out on paper as a set of gates and flip flops?

 

[ellis91]

I think think yiou're jumping too far ahead without understanding the digital logic fundamentals. You would never have more than one state transition in a signle clock cycle because you only change states based on various inputs when the clock rises (ie. 1 check per clock).

Have you tried working this circuit out on paper as a set of gates and flip flops?

.. I've oly been exposed to c++ and c.. i've just begun learning vhdl and verilog..

i'm aware that the state changes to the next state in this code everytime it comes across a rising edge.. i was asking if there was a technique to make it move across multiple states in one clock cycle.. without havin to merge all the states into a single.. that beats the purpose of designing a state machine..

 

[FvM]

I don't think, that it's a good idea to define output signals of your design as inout. If you did this, because you are reading the output ports insice your entity, you should either use the buffer type or an intermediate signal copied to the output ports. If you however intend to set these signals in another design entity concurrently, you most likely cerate a "multiple driver" fault.

the data value of byte_count has already changed

Shouldn't be a serious problem. You'll know the new value as well as the old one.

 

[TrickyDicky]

You can do plenty of things in VHDL. It doesnt mean you're describing a synthesisable circuit though. hence the reason I suggest you try to draw the logic circuit before writing any VHDL. I get the feeling you have very limited digital logic knowledge. Moving away from VHDL would help you immensly.