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VHDL generics question - an error occurs

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dohzer

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vhdl generics

I'm declaring the following interface and getting the following error:

Code:
entity entity_a is
	generic 
	(
		SIG_A_WIDTH 		: integer := 16;
		SIG_B_WIDTH 		: integer := 2;
		SIG_C_WIDTH		: integer := SIG_WIDTH_A - SIG_WIDTH_B;
	);

	port 
	(
		...
		blah
		...
	);
end entity_a;

Code:
Object 'sig_a_width' cannot be used within the same interface as it is declared

I want to be able to define "SIG_C_WIDTH" as a function of the other two widths, so is there an easier and/or more correct way to do it? Should I be declaring it in a separate package or somewhere else in the code?
 

FvM

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VHDL generics question

Yes, a package is the only option, it can be also placed in the same file as the entity
 

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