wtr
Full Member level 5
Hello all,
I have a situation where every state bar one requires a specific condition. I want an elegant solution to avoid having to place my condition in every state. The stuff below works, but it feels messy.
The less messy, but requiring more typing method is below
Since I'm absurdly lazy, I want the first solution because it requires less typing, but it feels wrong. I fear the synthesis would create a gated clock fsm. Does anyone have any recommendation for good spell design?
Wes
I have a situation where every state bar one requires a specific condition. I want an elegant solution to avoid having to place my condition in every state. The stuff below works, but it feels messy.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 if rising_edge(clk) then if rst then --stuff else --default signal assignments if majority_of_the_time_condition then case state is when 1 => do_stuff <= y; state <= 1; when 2 => do_stuff <= x; state <= 3; when 3 => -- majority condition statement doesn't apply; end case; end if; if state = 3 then do the stuff on this clock like padding end if; end if; end if
The less messy, but requiring more typing method is below
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 if rising_edge(clk) then if rst then --stuff else --default signal assignments case state is when 1 => if majority_of_the_time_condition then do_stuff <= y; state <= 2; end if when 2 => if majority_of_the_time_condition then do_stuff <= x; state <= 3; end if when 3 => do the stuff on this clock like padding end case; end if; end if; end if
Since I'm absurdly lazy, I want the first solution because it requires less typing, but it feels wrong. I fear the synthesis would create a gated clock fsm. Does anyone have any recommendation for good spell design?
Wes