VHDL allows process local variables. This is very useful if "majority of the time condition" has multiple terms. Then it ends up looking like case 1, even for complex expressions.
This code looks mostly fine to me though. There are some people who will put only state-change logic inside of the switch, and then have output logic in another structure. Without the actual code, it is hard to give an informed decision though.
I have a rule that if I feel I'm making a decision that makes the code "unclean" that I will add a comment to say that it is intentional. I will explain the intent and why the coding style provides a benefit. This allows you to explain why you did this, and readers can determine that you didn't just make a mistake while writing the code. A year later, you'll also know why you did something that (even as you are writing the logic) looks like a logic error. It also forces you to be honest -- you can't "design by simulation" when you have to provide an explanation. It also forces you to avoid being dangerously creative as you have to do more work to write weird code.
I also suggest finding a good editor. I typically don't care about typing and code length because I make rigorous, structured use of marker-based code-folding. I consider this feature to be as necessary as syntax highlighting.