entity .... is
port(
FREQIN: in std_logic;
7SEG : out std_logic_vector(7 downto 0);
DIGITS: out std_logic_vectot(3 downto 0);
);
end ....
signal frequencyin : std_logic;
signal 7segoutputDigit0: std_logic_vector(7 downto 0);
signal 7segoutputDigit1: std_logic_vector(7 downto 0);
signal 7segoutputDigit2: std_logic_vector(7 downto 0);
signal 7segoutputDigit3: std_logic_vector(7 downto 0);
signal counter : std_logic_vector(1 downto 0);
signal digiton : std_logic_vector(3 downto 0);
signal output : std_logic_vector(7 downto 0);
.... frequency measurement code
.... measured frequency -> BCD
---- BCD -> 7segment (7segoutputDigitx)
-- This clock should be a clock that has the frequency of the multiplexing
-- rate. If every digital has to be 'refreshed' 100 times as second then
-- this clock should be 400 hz (4 outputs...)
process (muxclk)
begin
if rising_edge(muxclk)
counter <= counter + 1;
end if;
end process;
-- 7 segment output
output <= 7segoutputDigit0 when (counter = "00)
else
7segoutputDigit1 when (counter = "01)
else
7segoutputDigit2 when (counter = "10)
else
7segoutputDigit3 when (counter = "11);
-- The multiplexer output is probably also needed 'externally' so
-- the hardware knows were 'output' should go to.
-- In case we need individual outputs for the multiplexer
digiton(0) <= '1' when (counter = "00")
else
'0';
digiton(1) <= '1' when (counter = "01")
else
'0';
digiton(2) <= '1' when (counter = "10")
else
'0';
digiton(3) <= '1' when (counter = "11")
else
'0';
-- The 'real' inputs/outputs
-- Always a good idea to work 'internally' with signals and then pass them
-- on to the actual inputs/outputs. This allows easy conversion when inverted
-- inputs/outputs are used. Internally we then always work with high level ('1')
-- active signals ...
DIGITS <= digiton;
7SEG <= output;
frequencyin <= FREQIN;