VHDL- Floating Numbers with STD_LOGIC_VETOR

[jose2]

To All;


How can I manage a floating number using STD_LOGIC_VECTOR?
For example (0.75 - 1.00) = -0.25.
How that operation can be represented using STD_LOGIC_VECTOR?


Thanks in advance;

JEM

 

[Tan]

You can declare it in variable or constant.however,real is not synthesizable.You can just simulate the result and see.

 

[FvM]

I remember, that you have started a similar thread some weeks ago and I think, I mentioned possible float representations Generally, the problem hasn't to do with std_logic_vector. That's just an array of bits, that can represent everything but doesn't give any information about the underlying number format. You have to decide about a suitable number format for your application, e.g. IEEE single precision and use a float library from your FPGA vendor or a second party, or the IEEE float package mentioned in your previous thread, or design something on your own.

however,real is not synthesizable

That's correct, if you think of ieee.math_real library.