VHDL FF based memory array

[shaiko]

Hello,

When I have a FF based memory array and I want to bring it's ports to the entity's output - I concatanate all the memory cells to a single long vector of length: memory_depth * memory_width

But is it possible to define the entity I/Os themselves as a 2D array ?

 

[TrickyDicky]

Yes. You'll have to declare the type in a package though.

 

[shaiko]

Please elaborate.

Can you show an example please...

 

[TrickyDicky]

package types_package is 
  type 2d_array_t is array(natural range <>, natural range <>) of integer;
end package;

use work.types_package.all;

entity some_ent is 
  generic(
    MEMORY_DEPTH : natural;
    MEMORY_WIDTH : natural
  );

  port (
    regs : out 2d_array_t(0 to MEMORY_DEPTH-1, 0 to MEMORY_WIDTH-1)
 );
end entity;

 

[shaiko]

THANKS TrickyDicky !

BTW ;
Does Verilog has this type as a standart ?

 

[TrickyDicky]

I dont know a lot about verilog, but afaik standard verilog limits arrays to 2d (its limitless in VHDL). SystemVerilog removes this restriction.

 

[shaiko]

But only 2D's are synthesizable...yes, I know that.

What I meant is:
Per your explanation I see that an array IO isn't a standart type in VHDL - and requires a type def to work...I asked if array IOs in Verilog are a standart feature of the language?