VHDL error with techbench

[souicabc321]

A question of VHDL

This is a design of VHDL

Library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;


Entity SRAM1 is
Port(
clk,cen,wen : in std_logic;
addr: in unsigned(6 downto 0);
din : in unsigned(31 downto 0);
dout: out unsigned(31 downto 0)
);
End SRAM1;

architecture syn of SRAM1 is

type ram_type is array (127 downto 0) of unsigned (31 downto 0);
signal RAM : ram_type:=(others=>(others=>'0'));
begin
process (clk)
begin
if clk'event and clk = '1' then
if cen='0' then
if wen ='0' then
RAM(to_integer(addr)) <= din;
else
dout <= RAM( to_integer(addr));
end if;
else

dout <= (others => 'Z');
end if;
end if;
end process;


end syn;

And this is a techbench of this design

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;



entity TB_ADDER IS
end TB_ADDER;
architecture TEST of TB_ADDER is
component SRAM is
Port( clk, cen,wen : in std_logic;
addr: in std_logic_vector(6 downto 0);
din : in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0) );
End component;
signal clk_i, cen_i,wen_i : std_logic;
signal addr_i : std_logic_vector(6 downto 0);
signal din_i,dout_i : std_logic_vector(31 downto 0);

begin
DUT: SRAM port map (clk_i, cen_i,wen_i,addr_i,din_i,dout_i);
process begin
clk_i<="0";
wait for 5ns;
clk_i<="1";
wait for 5 ns;
end process;
STIMULUS: process
begin
cen_i<="1";
wen_i<="0";
For i in 0 to 127 loop
addr_i <= i; din_i<= i;
wait for 10 ns;
End loop;
Wen_i<="1";
For i in 0 to 127 loop
addr_i <= i;
wait for 10 ns;
End loop;
end process STIMULUS;
end TEST;

However,the techbench is error.

Please teach me how to correct it.

 

[vipinlal]

Re: A question of VHDL

See this link:



--vipin
https://vhdlguru.blogspot.com/