VHDL - Equivalent statement

[carrot]

vhdl rising_edge

Hi ,

In VHDL, the statement - clk'event & clk='1' is not synthesizable, so what is the equivalent statement that can be replaced if it has to be synthesized

 

[smith_kang]

vhdl when statement

kindly go through this page
https://www.sandstrom.org/systemde.htm

 

[visualart]

vhdl or statement

Do you sure the statement can't be synthesizable?
I don't try it on the DC2005 plat, But i think it can be syntheisis

 

[silencer3]

synthesizable statements in vhdl

i think u should write, clk'event AND clk='1'. Then this is synthesizable. pls check ur code.

 

[xysafety]

synthesizable statement in vhdl

Yes, It can be synthesized.
And you can using the statement rising_edge(clock) to replace it.

 

[truebs]

clkevent not synthesizable

The above mentioned statement is synthesizable ...but in case you are having problems doing so...Please refer to the compiler manual of the compiler you are using ...and check out if it supports....

The problem in your case, it think is about the tools or the device you are using...

 

[farhada]

vhdl rising_edge( event

I agree with trubes, xysafety and silencer3,

I never used &, maybe that is your problem. I have been using it for years. I personally like the rising_edge(clock), but a lot of companies have a coding style that request 'event and ='1' instead.

Best regards,
/Farhad

 

[vlsi_whiz]

vhdl equivalence

The & operator should not be confused with the AND operation in VHDL. The & operator is meant for concatenation in VHDL whereas for the ANDing operation you should only use "AND".

One more thing, not all signal attributes are synthesizable in VHDL and certain attributes can only be used for Clock signals.

The 'Event and rising_edge() attributes are completely synthesizable and supported by all known VHDL tools and compilers without which we would not be able to design proper digital circuits be it combinational or sequential.

 

[deva_eda]

rising_edge attribute in vhdl

Carrot,

Even if you are facing problem after using the "AND" instead of "&", then check if you are using any contracdictory static expression in the process.

For example you might be checking for the rising edge in one line and you might be checking for if that particular signal is of value '0'.

-Deva

 

[sp]

vhdl equivalence

to use rising_edge(clk) and falling_edge(clk) please make sure u include the ieee.std_logic_1164.all

there are many compiler tht are different... in my course i take in my university, the **** textbook mention tht sensitivity list is not synthesizable... i still hav no idea y he mention so....

mayb diff compiler... i am using altera software n everthing seems fine so far...

regards,
sp