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[SOLVED] VHDL Equivalent of Verilog Code

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hareeshP

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Hi,
Please anyone tell me the VHDL equivalent for the below verilog code.


Code Verilog - [expand]
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assign  ifc_cle = (cpu_rst_n & (~rst_hold_f) & ((req_md_r == 2'b11)? req_rst_r : 1'b1))? 1'bz : (boot_override_r? rcw_src_r[8] : 1'bz);

 

TrickyDicky

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You are trying to translate some really badly written Verilog. I suggest you find a better source, or a Verilog tutorial/reference book. Or better still - understand what you're trying to do and write your own.

Im going to give a direct translation, written in equally bad formatting (though I assume you'll just copy and paste anyway, rather than try and understand it):


Code VHDL - [expand]
1
ifc_cle <= 'Z' when cpu_rst_n = '1' and rst_hold_f = '0' and ( (req_md_r = "11" and req_rst_t = '1') or req_md_r /= "11" ) else rcw_src_r(8) when boot_override_r = '1' else 'Z';



- - - Updated - - -

and here is the improved VHDL 2008 version:


Code VHDL - [expand]
1
ifc_cle <= 'Z' when ??(cpu_rst_n  and not rst_hold_f) and ( (req_md_r = "11" and ??req_rst_t ) or req_md_r /= "11" ) ) else rcw_src_r(8) when ??boot_override_r else 'Z';

 

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