VHDL equivalent of the Verilog

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Newbie level 1
Hi All

My top level design is in VHDL and my block modules are in verilog. I was trying to instantiate a verilog module in VHDL by writing VHDL wrapper for it by instantiating component form in top level module for the verilog block.

'define MEM_RST
module memory ( clk,
ifdef MEM_RST
rst,
endif
wr_bar,
data_input,
data_output);

COuld anyone tell me how I must translate the `ifdef when I write the component form for the above module?? I looked up and I understand that if generate is to be used if the ifdef was present in the architecture. Since this is present in module declaration, I am having trouble with the instantiation.

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