It probably depends on the user. I do the vast majority of my coding in Vim, but do switch back to Vivado to do elaboration and synthesis. Modelsim for simulation.
Typically I start new code by doing many small synthesis runs that aren't actually intended to be full functional designs. Just enough to show approximate area/performance and to see what possible resource issues occur. As you learn what can be synthesized, the need to do synthesis to see if some code construct works will be reduced.
I also use vim heavily. you can get gvim in windows as well, but you have to fix parts of it. Some people like emacs, sublime, or notepad++. I couldn't get marker-based code-folding to work in Notepad++, so I don't use it for VHDL/Verilog.
If you use windows command line, remember that you can set the width of the terminal by right clicking on the title bar and selecting "properties". The layout tab has options for width and some other stuff.