vhdl dpi dac with DE1-SOC Board

[jimmykk]

Hi
i need some help with communicating to SPI DAC 5641 THROUGH DE1 SOC ALTERA board, in vhdl. i have written some code but it is not working. i have to send 14- bit digital data from FPGA and obtain analog voltage at off board DAC OUTPUT. i am using GPIO bus to get the outputs on oscilloscope.

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Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity waveforms is 
port( 
      CLOCK_50      : in  std_logic;  
      --cs       : out std_logic;  
     -- sck      : out std_logic;   
        --sdi      : out std_logic
        --GPIO_1  : INOUT STD_logic_vector(0 DOWNTO 0) := "1";
        GPIO_1     :     INOUT STD_LOGIC_vector(35 DOWNTO 0)
        --GPIO_1[1]     : inout std_logic := '0';
        --GPIO_1[2]     : inout std_logic := '0';
     -- GPIO_1[3]     : inout std_logic := '0'
 
        );  
end waveforms;
 
architecture Behavioral of waveforms is
 
-signal turn     : std_logic := '0';   --*
signal data : std_logic_vector(0 TO 15) := "0011110011001100";     -- := X"3FFF";
begin
 
process(CLOCK_50)
 
variable i,k:integer:=0;
begin
if (falling_edge(CLOCK_50)) then
 
i:=i+1;
 
 
if i<65 then
GPIO_1(0)<='0';
else 
GPIO_1(0)<='1';
end if;
 
 
if i<3 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<5 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
k:=k+1;
 
elsif i<7 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<9 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
 
elsif i<11 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<13 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
 
elsif i<15 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<17 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
 
elsif i<19 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<21 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
 
elsif i<23 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<25 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
 
elsif i<27 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<29 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
 
elsif i<31 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<33 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
 
elsif i<35 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<37 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
 
elsif i<39 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<41 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
 
elsif i<43 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<45 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
 
elsif i<47 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<49 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
 
elsif i<51 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<53 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
 
elsif i<55 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<57 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
 
elsif i<59 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<61 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
 
elsif i<63 then
GPIO_1(1)<='0';
GPIO_1(2)<=data(k);
elsif i<65 then
GPIO_1(1)<='1';
GPIO_1(2)<=data(k);
K:=k+1;
elsif i = 127 then
i := 0;
end if;
end if;
end process;
 
 
GPIO_1(3) <= turn;
end Behavioral;

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How do you expect this to work? It's not even written in a way that describes hardware. VHDL is a hardware description language, you've written this like software. I'm not even going to try and figure out what you are trying to do.

Besides that you say it doesn't work, what doesn't work? You aren't being very specific about your problem.