I've been assigned to program a VHDL code for a 4bit down counter using half/full subtractors. I've got the sample testbench from my supervisor as shown below.
Counter testbench:
library ieee;
use ieee.std_logic_1164.all;
entity mycounter_testbench4 is
end mycounter_testbench4;
architecture mycounter_tb4 of mycounter_testbench4 is
signal count: std_logic_vector(3 downto 0);
signal clk: std_logic:='0';
signal reset: std_logic;