VHDL division for type real

[shaiko]

Hello,

The VHDL "/" operator definition in the numeric_std library:
(https://www.csee.umbc.edu/portal/help/VHDL/packages/numeric_std.vhd)
isn't defined for type "real".

However, when I apply it in Modelsim for dividing 2 real numbers - it works without errors.

Why ?

 

[TrickyDicky]

Because the numeric_std library has nothing to do with the real type. The real type is defined as part of the std.standard library.

 

[shaiko]

Having trouble finding it.
Can you please post a link to this library?

 

[ads-ee]

It should be in a directory on you PC if you have installed Modelsim/Xilinx-Vivado/Xilinx-ISE.

e.g. for Vivado:

Xilinx\Vivado\2016.2\data\vhdl\src\std\standard.vhd

 

[shaiko]

Thanks,

What I'm really trying to find is how the "/" operator is defined for type "real"
I.E:

What happens when the Left side is "real" and the right is "unsigned",
What happens when the Left side is "signed" and the right is "real"...etc.

Where can I find these ?

 

[TrickyDicky]

Thanks,

What I'm really trying to find is how the "/" operator is defined for type "real"
I.E:

What happens when the Left side is "real" and the right is "unsigned",
What happens when the Left side is "signed" and the right is "real"...etc.

Where can I find these ?

Those functions dont exist. You will have to create them for yourself.

- - - Updated - - -

std.standard defines some basic parts of the language. It contains the types integer, real, boolean, character, bit, bit_vector, string and time.
Integer, real and time are "implementation defined" meaning it is up to the tool/os as to how they work, and I think therefore all of the underlying code for them is therefore implicit ie. there is no VHDL for how they work.

The same is also true for the READ, WRITE, ENDFILE, FILE_OPEN, FILE_CLOSE and DEALLOCATE procedures.

- - - Updated - - -

And just confirming with the LRM - pretty much all of std.standard is commented out - meaning implicitly declared, including all of the arithmetic functions for real, integer and time:

The operations that are predefined for the types declared for package STANDARD are given in comments
since they are implicitly declared. Italics are used for pseudo-names of anonymous types (such as
universal_integer), formal parameters, and undefined information (such as implementation_defined).

 

[shaiko]

Those functions dont exist. You will have to create them for yourself.

Well, when I use (in Quartus or Modelsim) the "/" operator on "real" arguments - it works without errors.
Are you saying that it may work in different ways on both tools ?

 

[FvM]

What happens when the Left side is "real" and the right is "unsigned",
What happens when the Left side is "signed" and the right is "real"...etc.

I wonder in which situations the combination would be required in synthesizable VHDL? Real is only applicable for compile time calculations, e.g. initialization of constants or ROM tables. The arguments are usually integer and real numbers. If it makes any sense, signed and unsigned can be converted to integer in the calculation.

- - - Updated - - -

I reviewed the extensive real arithmetic I'm doing in my CIC core, it uses integer and real. Integer has to be converted to real before being combined with real variables.

 

[TrickyDicky]

Well, when I use (in Quartus or Modelsim) the "/" operator on "real" arguments - it works without errors.
Are you saying that it may work in different ways on both tools ?

Please post a code example.
real / unsiged an vice versa not possible with IEEE packages.

real/real is defined in std.standard, and is implicitly declared. Therefore its down to the tool how it works based, based on IEEE standards for floating point types. The way it works is immiterial, because 1.0 / 2.0 will always result in 0.5, no matter how it is defined underneath.

Remember, real types have no bitwise definition.

 

[shaiko]

Please post a code example.
real / unsiged an vice versa not possible with IEEE packages.

I'm sorry,
I meant real/positive and real/real...
From what you say I understand that real/real is well defined by the standard but real/positive isn't. Correct?

 

[FvM]

It's well defined with additional type conversion, e.g.:

real_var2 := real_var1 / real(int_var);

 

[shaiko]

It's well defined with additional type conversion, e.g.:
real_var2 := real_var1 / real(int_var);

This is exactly what I'm asking...is the casting absolutely necessary ?
Won't this also work?

real_var2 := real_var1 / int_var;

 

[TrickyDicky]

This is exactly what I'm asking...is the casting absolutely necessary ?
Won't this also work?

real_var2 := real_var1 / int_var;

Yes it is necessary - remember VHDL is strongly typed.

real_var2 := real_var1 / int_var;
wont work because real/int is not defined

- - - Updated - - -

std.standard does not define any functions for any interaction between types.