Yes, you will need to run synthesis for a post synth netlist and implementation for a post-layout netlist.
But why are you bothering? you'll probably spend more time getting it up and running than you could have being proper testing in stage 1 with work to test on the real hardware.
Its only really ASIC design where (2) and (3) are more important. I think they were used more often in FPGAs in the past, but since PCs, Tools and Techniques have got better, the requirement and usefulnes of 2 and 3 has reduced (in 12 years, I havent run a single post synth or layout simulation).