vhdl (counter and comparison) exercise

Status
Not open for further replies.
P

Pape_4

Newbie level 3
Joined
Sep 6, 2011
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Thessaloniki,Macedonia-Greece
Activity points
1,302
Hello I am new to forum.. I'm student and i have to solve an exercise with vhdl. Ι am trying to create a circuit that on the output brings the pattern 0000111100001111.. with a clock input!

My first thought was to create a counter mod3!

I await your answers!

Thank you!
 

If you become a little more sense would be better! I'm still low on digital design! and not understood very well what you mean!

Thank you for your interest and prompt reply!
 

create a counter, connect output to bit 2

Code: 
signal counter : unsigned(2 downto 0);

process(clk)
begin
  if rising_edge(clk) then
    counter <= counter + 1;
  end if;
end process;

output <= counter(2);
 
Reactions: Pape_4

    P

    Pape_4

    Points: 2
    Helpful Answer Positive Rating
-1 instead of +1

---------- Post added at 20:40 ---------- Previous post was at 20:39 ----------

and start the counter at "111"
 
Reactions: Pape_4

    P

    Pape_4

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…