VHDL: converting 64bit vector to 32bit vector

[MagixD]

Hello,

I want to multiply two 32bit vectors and add a 32bit vector to it. As we know, if we multiply two 32bit vectors the result is a 64bit vector. I know that the result of the multiplication in my design will not exceed 32bit, so i wrote a code in a style like this:

signal arr1 : signed(31 downto 0);
signal arr2 : signed(31 downto 0);
signal res  : signed(63 downto 0);
signal foo  : signed(31 downto 0);

res <= arr1*arr2;

foo <= res(31 downto 0) + X"0000000F";

Is it possible to write the code without the use of the signal res, like:

foo <= (arr1*arr2)(31 downto 0) + X"000000F";

I hope anyone can understand my problem.

magixD

 

[flanix]

you can try this:
add signal
signal temp : signed(63 downto 0);
temp(31 downto 0) <= "00000000000000000000000000001111"

foo <= res + temp;

 

[FvM]

In VHDL, you can't construct slices of expressions.

You can define a function, that returns the intended bit selection. With numeric_std library, you can use the resize standard function, it would also provide saturation logic, if the input signal range is not limited in a suitable way.

I don't understand, why you want do downsize the product to 32 bit and then add a 64 bit signal?

 

[MagixD]

@flanix:
Thanks for your answer, but i think you didn't really get my problem.

@FvM:
What i want to do is multiply two 32bit vectors, assign the result to a 32bit vector and than add a 32bit vector. My compiler and, as far as i know VHDL itself, longs for a 64bit vector as result of the multiplication (that's clear, becaus only a 64bit vector can store all possible results of a multiplication of to 32bit vectors).
I know that the multiplication won't exceed 32bits, so what I do now is:

signal arr1 : signed(31 downto 0);
signal arr2 : signed(31 downto 0);
signal res  : signed(63 downto 0);
signal foo  : signed(31 downto 0);

res <= arr1*arr2;

foo <= res(31 downto 0) + X"0000000F";

That works fine, but i thought to myself that i would be nice to write the calculation in one single line and restrain "arr1*arr2" to the lower 32bits. So I don't need such a function by design but by code-clarity (i have much more of this constucts in my code).

I was afraid that this is not possibly, since i searched my VHDL books in advance, of course.

Thanks to both of you.

best regards,
magixD

 

[lucbra]

If you know in advance that the result of the multiplication will not exceed 32-bit, this means that both multiplier and multiplicand need no more than 16-bit.

The expression that you used (arr1 * arr2) is therefore throwing away resources.

you would rather use something like:

foo <= (arr1(15 downto 0) * arr2(15 downto 0)) + X"000F";