VHDL convert to Verilog

Code VHDL - [expand]
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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE STD.TEXTIO.ALL;
USE IEEE.std_logic_TEXTIO.ALL;
 
ENTITY std_logic_ram IS
   PORT (address : IN std_logic_vector; 
         datain : IN std_logic_vector; dataout : OUT std_logic_vector;
         cs, rwbar : IN std_logic; opr : IN BOOLEAN);
END ENTITY std_logic_ram;
 
ARCHITECTURE behavioral OF std_logic_ram IS
   TYPE mem IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) of std_logic;
 
   PROCEDURE init_mem (VARIABLE memory: OUT mem; 
                       CONSTANT datafile: STRING) IS
      FILE stddata : TEXT;
      VARIABLE l : LINE;
      VARIABLE data : std_logic_vector(memory'RANGE(2)); 
    BEGIN
      FILE_OPEN (stddata, datafile, READ_MODE);
      FOR i IN memory'RANGE(1) LOOP
         READLINE (stddata, l); READ (l, data);
         FOR j IN memory'REVERSE_RANGE(2) LOOP
            memory (i,j) := data(j);
         END LOOP;
      END LOOP;
   END PROCEDURE init_mem;
 
   PROCEDURE dump_mem (VARIABLE memory: IN mem; 
                       CONSTANT datafile: STRING) IS
      FILE stddata : TEXT;
      VARIABLE stdvalue : std_logic;
      VARIABLE l : LINE;
   BEGIN
      FILE_OPEN (stddata, datafile, WRITE_MODE);
      FOR i IN memory'RANGE(1) LOOP
         FOR j IN memory'REVERSE_RANGE(2) LOOP
            stdvalue := memory (i, j); 
            WRITE (l, stdvalue);
         END LOOP;
         WRITELINE (stddata, l);
       END LOOP;
   END PROCEDURE dump_mem;
 
BEGIN
 
   PROCESS 
      CONSTANT memsize : INTEGER := 2**address'LENGTH; 
      VARIABLE memory : mem (0 TO memsize-1, datain'RANGE);
   BEGIN
      id: IF opr'EVENT THEN
         IF opr=TRUE THEN init_mem (memory, "memdata.dat");
         ELSE dump_mem (memory, "memdump.dat");
        END IF;
      END IF;
      wr: IF cs = '1' THEN 
         IF rwbar = '0' THEN -- Writing
            FOR i IN dataout'RANGE LOOP
               memory (conv_integer (address), i) := datain (i);
            END LOOP;
         ELSE                -- Reading
            FOR i IN datain'RANGE LOOP
               dataout (i) <= memory (conv_integer (address), i);
            END LOOP;
         END IF;
      END IF;         
      WAIT ON cs, rwbar, address, datain, opr;
   END PROCESS;
 
END ARCHITECTURE behavioral;