VHDL concatenation operator (&) with INTEGER type

[omara007]

vhdl concatenation

hi guys

how to concatenate integer elements the same way std/bit elements are concatenated using (&) ? .. given that (&) doesn't work with integers

 

[omara007]

concatenation in vhdl

Any idea ?

 

[Marcel Majoor]

concatenation operator in vhdl

If you convert the integer to a vector then you can do it, like the following example shows:

signal   test    : std_logic_vector(31 downto 0);
constant inttest1: integer := 1234;
constant inttest2: integer := 1234;


  -- conv_std_logic_vector(number, nr_of_bits)
  test <= conv_std_logic_vector(inttest1, 16) & conv_std_logic_vector(inttest2, 16);

 

[vipinlal]

general uses of concatenation operator is explained here..
https://vhdlguru.blogspot.com/2010/03/concatenation-operator-in-vhdl.html