VHDL component instantiation from 2 different places

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shaiko

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Hello,

Is it possible to instantiate a VHDL component from 2 different entities?
Some signals are used only in one entity and the remaining signals are used only by the second...
 

Not the same instantiation no. You'll have to provide all IO inside one entity.
 
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    shaiko

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That's an interesting language restriction. What about Verilog?
 

Not really that interesting, or that useful, and never a situation Ive ever seen anyone complain about. Afaik you cannot do it in any HDL (I dont think you can call half a function in C either!)
If you think of the design using the simile of circuit components, how would you expect to connect half a chip on one board and half a chip on another board? how would the two halves communicate? You might get around what you want to do with Global signals, but Altera will refuse to compile them (they are only really meant for simulation, and IMO, with the new hierarchical signal name access in VHDL 2008 almost completly redundant - also intended for simulation).
 
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    shaiko

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You must instantiate the component outside of the 2 entities and use ports to connect to it, or instantiate the component in one of them and connect the unused part to ports to make it available for another block/entity.
 
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