process (IDC)
begin
if(rising_edge(IDC)) then
if(rising_edge(C)) then
if(Tee= '0') then
wait until ??;
end if;
Normally rising edges are used. If a signal is included in the sensitivity list of process, the process will be executed wherever there is a change in the included signal. Considering you are writing this process for a design that will be synthesized, you can writeinside a process how to wait for a rising edge or a falling edge ?
process(clk_i, rst_n_i)
begin
if rst_n_i = '0' then -- async reset signal
-- assign reset values of signals used;
elsif rising_edge(clk_i) then
-- write your logic here
end if;
end process;
You can, but when designing a hardware model which will NOT be synthesized. Normally this is done in test benches.or can we wait for certain fixed time ?
wait for 10 ns; -- wait for a flat time of 10 nanoseconds
wait until falling_edge(clk_i); -- wait until the falling edge of clk_i
wait until clk_i'event; -- wait until the rising or falling edge of clk_i
we have a idc clock , tff flipflop(half of the frequency of idc) and a carry signal which gets high with certain offset. I want to geerate a new tff signal(tff_new) such that
1. if the carry signal goes high when tff=1 , the tff_new would be inverted wrt to tff next rising edge of tff.
2. if the carry signal goes high when tff=0 , the tff_new would be inverted wrt to tff after second rising edge of tff
we have been failing to get this logic implemented .. please give us idea on how to approach it!View attachment 142489
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/13/2017 04:17:10 PM
-- Design Name:
-- Module Name: dco - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dco is
Port ( idc : in STD_LOGIC;
-- start: in STD_LOGIC;
tff : in STD_LOGIC;
c : in STD_LOGIC;
b : in STD_LOGIC;
tffnew : out STD_LOGIC;
idout : out STD_LOGIC);
end dco;
architecture Behavioral of dco is
shared variable temp : integer := 2;
begin
--process(start)
--begin
--tffnew <= tff;
--end process;
process(c)
begin
if(rising_edge(c)) then
if(tff='1') then
temp:=1;
end if;
if(tff='0') then
temp:=0;
end if;
end if;
end process;
process(tff)
begin
if(rising_edge(tff) or falling_edge(tff)) then
if(temp=0) then
tffnew <= not tff;
temp:=2;
elsif(temp=1) then
tffnew <= not tff;
temp:=2;
elsif(temp=2) then
tffnew <= tff;
end if;
end if;
end process;
-- --IDOUT <= (not IDC) and (not tffnew);
end Behavioral;
sir, i am a beginner and trying to model a dco . above code is something that i worked
inside a process how to wait for a rising egde or a falling edge ? or can we wait for certain fixed time ?
eg.
Code:process (IDC) begin if(rising_edge(IDC)) then if(rising_edge(C)) then if(Tee= '0') then wait until ??; end if;
Code VHDL - [expand] 1 2 3 4 process (clk) begin q <= d; end
Code VHDL - [expand] 1 2 3 4 5 6 process (clk) begin if (t) then q <= not q; end if; end
The nested clocks won't achieve useful behavior in simulation either. Notice that the inner rising_edge() event only becomes true if both clock edges occur in the same delta cycle, which is almost impossible.Also the above code is impossible to implement in any FPGA as you have two "clocks" in the process, i.e. rising_edge(IDC) and rising_edge(C).
my first post is a part of the second post.. i want to implement dco(second post with diagrams) , i could implement if i could use a way to delay it so asked the first post(on how to delay inside a process)...
i am not able to code to get the desired output of dco (explained in those two attachments).. i need help or idea to code dco for adpll (behaviour explained in the attachment above)
... i am not sure how to use dflipflop to get the desired output (my second post)... tflipflop is a previous block in my project so the input is named as tff..
hope this clears it!
Dear op,
Regardless of going down the rabbit hole regarding what flip flop you're using.
Consider the following
process with sensitivity list cannot have wait statements.
process without sensitivity lists can have wait statements.
You would use the wait on, wait until and wait for statements usually for testbenching because for the most part people consider it non synthesible.
However a single wait until statement can be synthesised because it's considered equivalent to a clocked process. - in some tools.
The wait on statement can be synthesised because some tools consider it to be the sensitivity list to a combinatorial process.
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