ethan
Member level 3
VHDL coding question
Hi all,
I have a question about using "process" and "if" statement. Can we use these two statements for describing a pure conbinational logic, say, a 2to1 mux? Will the code be synthesized as logic circuits with latches (therefore not combinational)? The following vhdl code went throught compile without any problems and get internal problem from Quartus II when simulated. Can anybody explain why?
By the way, the 2to1 mux is just used as an example, I actually use the if statement for a much complicated case which is easier when using embedded if statements.
Thank you.
library ieee;
use ieee.std_logic_1164.all;
entity mux2to1 is
port (a, b: in std_logic;
sel : in std_logic;
c: out std_logic);
end mux2to1;
architecture behavior of mux2to1 is
begin
bev: process (a,b,sel) is
begin
if sel='0' then
c <= a;
else
c <= b;
end if;
end process;
end architecture behavior;
Hi all,
I have a question about using "process" and "if" statement. Can we use these two statements for describing a pure conbinational logic, say, a 2to1 mux? Will the code be synthesized as logic circuits with latches (therefore not combinational)? The following vhdl code went throught compile without any problems and get internal problem from Quartus II when simulated. Can anybody explain why?
By the way, the 2to1 mux is just used as an example, I actually use the if statement for a much complicated case which is easier when using embedded if statements.
Thank you.
library ieee;
use ieee.std_logic_1164.all;
entity mux2to1 is
port (a, b: in std_logic;
sel : in std_logic;
c: out std_logic);
end mux2to1;
architecture behavior of mux2to1 is
begin
bev: process (a,b,sel) is
begin
if sel='0' then
c <= a;
else
c <= b;
end if;
end process;
end architecture behavior;