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VHDL coding questions about using process and if statements

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ethan

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VHDL coding question

Hi all,

I have a question about using "process" and "if" statement. Can we use these two statements for describing a pure conbinational logic, say, a 2to1 mux? Will the code be synthesized as logic circuits with latches (therefore not combinational)? The following vhdl code went throught compile without any problems and get internal problem from Quartus II when simulated. Can anybody explain why?

By the way, the 2to1 mux is just used as an example, I actually use the if statement for a much complicated case which is easier when using embedded if statements.

Thank you.

library ieee;
use ieee.std_logic_1164.all;

entity mux2to1 is
port (a, b: in std_logic;
sel : in std_logic;
c: out std_logic);
end mux2to1;

architecture behavior of mux2to1 is
begin
bev: process (a,b,sel) is
begin
if sel='0' then
c <= a;
else
c <= b;
end if;
end process;
end architecture behavior;
 

maksya

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VHDL coding question

What kind of problems during simulation do you mean? This project is compiled without any warnings. RTL View shows that no latches were generated.
 

ethan

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Re: VHDL coding question

Thanks for your reply. When I started to simulate the circuit in Quartus II, here is the error message I got:

Internal Error: Sub-system: SIM, File: sim_preprocessor.cpp, Line: 2532
machine_iname != 0
Quartus II Version 5.0 Build 148 04/26/2005 SJ Full Version

I got the same error for my controller design which uses the process and if, case statement a lot. Do you think it is something with my Quartus II simulator? But it works perfectly with my pure combinational VHDL codes. Can you try to simulate my code in your simulator?

Thank you.
 

kareemrefaat

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Re: VHDL coding question

Well I am not sure about the quartus error you are getting but I will answer some of your questions.A "process" with "if" statement will generate a combniational block.The synthesis tools will transform if statement to some multiplexers depending on how you wrote the code.Sequential process will be generated if there is a "clk" in your process. The synthesis tools will insert latches if one of your output or internal signals is not assigned in every branch of the "if" statment.Thus the best practice is to make "defaults" for all signal at the beginning of the process.
Regards,
Kareem
 

maksya

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VHDL coding question

I'm using Quartus 6.0. And neither during compilation nor simulation there are no errors or warnings. Your project is functioning correctly. IF operator in VHDL is sequential operator, and therefore you have to use it only inside the PROCESS operator. The synthesiser based on your code will generate something like a priority structure (for IF statement).

Maybe it will be usefull to make some changes in your code on this way -

...

bev: process (a,b,sel) is
begin

case sel is
when '0' => c <= a;
when others => c <= b;
end case;

end process;

...

Please try to compile and simulate it, and post the results of the experiment.
 

babaship

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Re: VHDL coding question

remove the is in the process, line

Added after 51 seconds:

library ieee;
use ieee.std_logic_1164.all;

entity mux2to1 is
port (a, b: in std_logic;
sel : in std_logic;
c: out std_logic);
end mux2to1;

architecture behavior of mux2to1 is
begin
-- bev: process (a,b,sel) is -----------------------######## is a problem here
bev: process (a,b,sel)
begin
if sel='0' then
c <= a;
else
c <= b;
end if;
end process;
end architecture behavior;
 

maksya

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Re: VHDL coding question

babaship said:
remove the is in the process, line
This is not an irreversible accident, just syntactic error =) Point is that I wrote this code in Quick Reply window. Moreover, it was in the small hours...
 

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