vhdl coding for pattern generation

[vishushru]

vhdl code to generate incremental pattern in serial manner using counter.
please help me out

 

[ads-ee]

So you need to send the contents of a counter as a serial stream? Is this supposed to be done LSB or MSB first?

I won't code this for you but here is the basic logic you will need to do this.

1) create a counter with an enable count input (this is the incrementing pattern you are sending)
2) create a counter that counts the bits sent (this is a counter that is big enough to count the width of the incrementing pattern counter)
3) make a loadable shift register to serially shift the loaded value out either LSB or MSB first.
4) combine the above stuff along with a check for the last bit sent to increment the pattern counter.
5) write a testbench to verify your design.

If you've already done some of this work already and are just having problems then post the code you've already written to get help.

 

[vishushru]

i wrote a vhdl code for 8 bit counter what i hav to do next

 

[ads-ee]

Steps 2 thru 5 in my previous post.

Let me add that step 4 also involves creating the top level file which either has instances of other code or the code of each function in that top file.