chaitu2k
Member level 3

vhdl slices
Hi all
does anyone have documents or tutorials realting to VHDL design for area (FPGA) i.e efficient slice utilization coding or how the code infers Slices, LUTs, CLBS etc....i need to learn how to code so as to optimize for area.........
thanks
Hi all
does anyone have documents or tutorials realting to VHDL design for area (FPGA) i.e efficient slice utilization coding or how the code infers Slices, LUTs, CLBS etc....i need to learn how to code so as to optimize for area.........
thanks