VHDL - Coding and Timing question

[vb_thecapt]

Hi everybody! I have a question about coding&timing/delay relationship.
Considering a code like this

for index 0 to MAX_N loop
varMatrix:= CONV_INTEGER(matrix(index));
diff := a-varMatrix;
if(diff < VAL) then
c:= coeff(diff);
else
c := 1;
end if;
prod := ker(index)*c;
...
end loop;

where i create a variable for every accessed array element , and considering this code

for index 0 to MAX_N loop
if( abs(a-CONV_INTEGER(matrix(index))) < VAL) then
prod := ker(index)*coeff( a-CONV_INTEGER(matrix(index)) );
else
prod := ker(index);
end if;
...
end loop;

where i use every time that i need the "whole" indexed-array element.
If these two codes have different hardware mapping, which of these two codes are faster?
Code 1 implies a register (thus a delay) for every created variable?
Code 2 implies only that a "wire" is taken from a source?
Sorry if it sounds a bit messy

 

[xtcx]

Hi everybody! I have a question about coding&timing/delay relationship.
Considering a code like this

where i create a variable for every accessed array element , and considering this code

where i use every time that i need the "whole" indexed-array element.
If these two codes have different hardware mapping, which of these two codes are faster?
Code 1 implies a register (thus a delay) for every created variable?
Code 2 implies only that a "wire" is taken from a source?
Sorry if it sounds a bit messy

I dont see any diff between two of your code. Both are same, in terms of hardware, it should be same too. Did you try running the tool?. And, I dont find any registers ofcourse.
You said "delay", where is the delay?. I dont see any delay though,

Can you specify?.

 

[vb_thecapt]

a variable isn't mapped into an hardware register?

 

[xtcx]

it is when clocked. You dont have a clocked circuit. Without a clock, no registers\DFF

 

[vb_thecapt]

Ops sorry....these are snippet code taken from a project which is clocked. example:

entity....
architecture..
begin
   process(CLK)
   begin
          ...
          previous code
          ...
   end process;
end architecture;

does this matters?

 

[std_match]

Ops sorry....these are snippet code taken from a project which is clocked. example:

entity....
architecture..
begin
   process(CLK)
   begin
          ...
          previous code
          ...
   end process;
end architecture;

does this matters?

It doesn't matter in this case. A variable only has a register if it is used to hold information from one clock cycle to the next. If you in each clock cycle assign a value to the variable before it is used, there is no register, and maybe not a physical signal at all. The compiler should optimize both your examples to the same circuit.

 

[xtcx]

process(clk)
variable a:std_logic;
variable b:std_logic;
variable c:std_logic;
begin

  if rising_edge(clk) then
     a := x;
     b := a;
     c := b;
 end if;
     y <= c;
end process;

In this case, it does not create 3 registers because you are not using data before next clock. You should be aware that variable can be compared to a wire....and can be a reg if used properly.

 

[vb_thecapt]

thanks..an example of using data before next clock would be?? thank you again

 

[xtcx]

I dont get your words.
In case if you are asking between successive 2 clocks,
Take the value of a,b it will be the same data before next clock ticks. But is you take value of C, it will be a registered data and hence you will get it after next clock only