VHDL code to a logic circuit

[daisyzari]

I'm having difficulty understanding this part of code that I've been using in my I2C project.

gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1'; --'0';
elsif (clk'event and clk = '1') then
if (cnt = 0) then
clk_en <= '1';
cnt <= clk_cnt; -- loading of clk_cnt when clk_en is disabled
else
if (slave_wait = '0') then
cnt <= cnt -1;
end if;
clk_en <= '0';
end if;
end if;

end process gen_clken;

I actually need to translate this code into a logical circuit. And so it is important that I understand this code.
Can anyone pls help me understand and translate this code into a logical circuit?

Thank you :grin:

 

[Alexium]

Why don't you synthesise the code and study the RTL scheme?
Besides, the code is pretty simple and straightforward. Is there some specific aspect you don't understand, or you need a full explanation?

 

[daisyzari]

Why don't you synthesise the code and study the RTL scheme?
Besides, the code is pretty simple and straightforward. Is there some specific aspect you don't understand, or you need a full explanation?

I did checkk the RTL of the code but I can't seem to understand it along with the code. It seems to be some sort of clock divider to another code but I don't how it works as a clock divider for that code. Can you please explain to us how the code works thank you very much.

 

[atulaxc]

Here is some explanation in blue, I have divided the code in three parts
Part 1 ----
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1'; --'0';
----------------------
At reset cnt = 0 and clk_en =1 is
----------------------
Part 2 -----
elsif (clk'event and clk = '1') then
if (cnt = 0) then
clk_en <= '1';
cnt <= clk_cnt; -- loading of clk_cnt when clk_en is disabled
else
-----------------
When not in reset then with every rising edge of clock load cnt with clk_cnt and keep clk_en 1
-----------------
Part 3 ---
if (slave_wait = '0') then
cnt <= cnt -1;
end if;
clk_en <= '0';
end if;
end if;
-------------------------
If not in reset and no rising edge on clock then decrement the cnt and clear clk_en = 0
--------------------------

 

[FvM]

-------------------------
If not in reset and no rising edge on clock then decrement the cnt and clear clk_en = 0
--------------------------

Please reconsider!

Although the code can be analyzed as such, I don't think it's reasonable to cut a small snippet from a project (an I2C controller from opencores.org) and ask for an explanation. If you know the meaning of the involved signals, it can be understood better. You also omitted comments around the code snippet. Finally, a project link should be given.

 

[Alexium]

-------------------------
If not in reset and no rising edge on clock then decrement the cnt and clear clk_en = 0
--------------------------

The explanation is wrong. You can't do something when there is "no rising edge", it doesn't make sense.

 

[atulaxc]

You can still decrement on negative edge of clock or have a counter which is pure combinatorial .. We need to first know the entire code to know it in details. Its quite possible that the printed code is not correct.

 

[FvM]

You can still decrement on negative edge of clock or have a counter which is pure combinatorial ..
..
Its quite possible that the printed code is not correct

The present code, which is a correct excerpt from a opencores project, is actually counting on rising edge. As already mentioned, I agree to your comment about posting more code.

I don't see however, how a "pure combinational counter" in synthesized hardware should work. I know, that asynchronous logic design exists as an alternative method to usual synchronous design. But it needs at least an enable signal with handshake to signal events.

A logic implementing your description

If not in reset and no rising edge on clock then decrement the cnt and clear clk_en = 0

won't be synthesizable and bring up an error message like "state of signal cnt[x] isn't preserved outside clock edges".