VHDL code Syn_Clear_set Counter?? pls give me some idea

[kyawsoelwin]

vhdl code for counter

Pls check it out this input wave vector file.



I want to design a counter which starts counting at which set pin=1 and positive rise edge of clock.
And Counting reset again next cycle of set pin.

if i used the code

if (set=1) then
if (clk'event and clk='1')

the counter counts only set cycle.

if i used the code

if (clk'evnt and clk='1')
cnt:=cnt+1; -- for counting the clk
if set='1' then
cnt=0 ---counter reset

If i tried again like that counting and reset is ok but .. it has no synchronization

the counting ignores the clk edges inside the set high cycle (set='1')

I tried a few couple of days. pls help me and give some idea.

thanks in advance for your time.

Regards,



The waveform of this problem's solution is as follow . pls click and see.



But I cann't design in VHDL to get this solution. If someone expert in VHDL , pls kindly help me and give some idea.

Thanks and regards again.

 

[kyawsoelwin]

vhdl code for counter design

Thanks a lot to all memebers who visit to my post.

I got it now!!

someone who interested in it, pls reply here!!
I will share to you in next post.