[SOLVED] VHDL code Need to be tested...

[amitjagtap]

hi All,
I have written a vhdl code for clk generation. I have simulated it on ISIM and Modelsim. It is synthesized too. But I dont have FPGA board to test it. Can anybody test it on their Kit and send me the result....

*********** VHDL Code ******************
entity clkgentest is
Port ( reset:in std_logic;
clkdivut std_logic;
clkout : out std_logic);
end clkgentest;

architecture Behavioral of clkgentest is

signal clk: std_logic:=('0');
signal clkby2:std_logic:=('0');
begin
clk<=not clk after 20 ns;
clkout<=clk;
process(clk) is
begin
if reset='0' then clkdiv<='0'; else
if (clk'event and clk='1') then clkby2<=not clkby2; end if;
end if;
clkdiv<=clkby2;
end process;

end Behavioral;

 

[alexan_e]

clk<=not clk after 20 ns;

This line can not be synthesized for hardware, it is only used to simulate a behavior in test bench, you can't add a delay in hardware.

Alex

---------- Post added at 15:45 ---------- Previous post was at 15:36 ----------

"Unsynthesizable Constructs

Certain VHDL constructs are unsynthesizable and simply cannot be used for synthesis. For example, the wait statement cannot be synthesized. Since FPGAs have no internal timers, the only concept of time FPGAs have is from their clock inputs. Clock speeds can vary based on implementations, so wait statements cannot be synthesized. The best way to do timing in VHDL designs is to use a clock divider or simply to count clock cycles."

The only hardware synthesizable wait is the following in a process with no sensitivity list.
Also note that only one wait statement can exist in a process.

process(CLK)
begin
  if rising_edge(CLK) then
    Q <= D;
  end if;
end process;

[B]process
begin
  wait until CLK='1';
  Q <= D;  
end process;[/B]

Alex

 

[amitjagtap]

Yes I was in doubt, but the code is not giving any error in synthesize. thats i forced to put this on forum.
Actually I m interested to see somebodies log report for this code ...If no errors then tested result on FPGA kit.

 

[alexan_e]

You can download and install Xilinx ISE or Altera Quartus II , these are free.

here is the log of ISE 11 and synplify for spartan3 and 3E

Alex

 

[FvM]

If no errors then tested result on FPGA kit.

And your next question will be: "Why I don't get any output from my design?"
But Alex has already answered it.

The way XST tells about this issue is rather laconic:

All logic was removed from the design.

 

[alexan_e]

The "Unsynthesizable Constructs" part was from an Internet source and was saying that "wait" cannot be used for hardware synthesis at all
so i had to give the "wait for" example because this specific "wait" can be used.

"Wait until is usually understood by the synthesis tools as equivalent to if rising_edge"
I thought that Wait until would be more like a while loop,
if i understand correctly you are saying that it is translated in an if rising_edge(clk) statement with the rest of the process code inside the if.

will this code be triggered only in a rising edge of a signal?
For example if there is a value1<=value2 after the "wait until" it will only be executed at rising edge of the clk or will it be constantly evaluated while clk='1'?

I have never used "wait" it in my code so I'm not sure.

Alex

 

[FvM]

Sorry, I deleted my supplement, because I found, that you completely answered the question, when saying, only a specific form of wait is allowed for synthesis. I had overlooked this previously.

will this code be triggered only in a rising edge of a signal?

Yes, it's creating synchronous registers like rising_edge.

I have never used "wait" it in my code

That's reasonable, it's of no particular use in synthesized code.