VHDL code for T-Flip Flops

[e.the]

hi,
I want to write a VHDL code for this design. can you help me with that?
regards

 

[andre_luis]

Check if this is what you need:

https://www.edaboard.com/threads/77216/#post338311




+++

 

[e.the]

thats the issue. i'm not sure this is what i need, but thanx.

 

[aruipksni]

thats the issue. i'm not sure this is what i need, but thanx.

check this out :

[syntax=vhdl]
library ieee;
use ieee.std_logic_1164.all;


--------------------------------------------------------------------------------
entity  tffs is
  generic (
    n : natural := 4); 
  port (
    Clk      : in  std_logic;
    clr_n      : in std_logic; 
    e   : in  std_logic;
    q   : out std_logic
	
    );            
end entity tffs;
--------------------------------------------------------------------------------

architecture Bhv of tffs is

dn, qn, qno : std_logic_vector(0 to n-1);

begin
 
 --in
 dn(0) <= e;
   
 --combinatoric  
 gen_more_then_2ffs : if n >=2 generate 
   gen_i : for i in 1 to n-1 generate 
   
     dn(i) <= dn(i-1) and qno(i-1);
   
   end generate gen_i;
 end generate gen_more_then_2ffs;
 
 --out
 q <= qno(n-1); 
 
 -- tffs
 gen_in : for i in 0 to n-1 generate 
 
   p_clk : process(clk)
 
   begin
     if rising_edge(clk) then
	   if (dn(i) = '1') then
	     qn(i) <= not qn(i);
	   end if;
     end if;
   end process p_clk;
 
 qno(i) <= qn(i) when clr_n = '1' else '0';
 
 end generate gen_in;
 
 
end Bhv;

[/syntax]

 

[vlsi_whiz]

--
-- D-Flip FLop 
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;

ENTITY dff IS
  PORT ( 
        clock  : IN  std_logic;
        reset  : IN  std_logic;
	    d      : IN  std_logic;
        q      : BUFFER std_logic
       );
END ENTITY dff;

ARCHITECTURE rtl OF dff IS
BEGIN
PROCESS ( clock, reset ) 
BEGIN
  IF ( reset = '0' ) THEN
     q    <= '0';
  ELSIF ( clock = '1' AND clock'EVENT) THEN
     q  <= d;
  END IF;
END PROCESS;
END rtl;


--
-- T-Flip Flop
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.dff;

ENTITY tff IS
  PORT (
        clock : IN     std_logic;
        clear : IN     std_logic;
		t     : INOUT  std_logic;
        q     : BUFFER std_logic
       );
END ENTITY tff;

ARCHITECTURE rtl_tff OF tff IS

COMPONENT dff 
  PORT (
        clock : IN  std_logic;
        reset : IN  std_logic;
        d     : IN  std_logic;
        q     : BUFFER std_logic
       );
END COMPONENT;

BEGIN

dff_inst : dff PORT MAP
                        (
                         clock => clock,
                         reset => clear,
	                     d     => NOT q,
                         q     => q
                        );
END rtl_tff;


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.tff;

ENTITY ckt IS
  PORT (
        enable : IN std_logic;
		  clock  : IN std_logic;
		  clear  : IN std_logic;
		  q_out  : BUFFER std_logic
		 );
END ENTITY ckt;

ARCHITECTURE rtl_ckt OF ckt IS

COMPONENT tff
  PORT (
         clock : IN     std_logic;
			clear : IN     std_logic;
			t     : INOUT std_logic;
			q     : BUFFER std_logic
		);
END COMPONENT;

SIGNAL t_2,t_3,t_4,q,q2,q3 : std_logic;

BEGIN


tff_1 : tff PORT MAP (
                      clock => clock,
							 clear => clear,
							 t     => enable,
							 q     => q
							 );
							 
t_2 <= enable AND q;
							 
tff_2 : tff PORT MAP (
	                   clock => clock,
							 clear => clear,
							 t     => t_2,
							 q     => q2
							 );
							 
t_3 <= t_2 AND q2;
							 
tff_3 : tff PORT MAP (
	                   clock => clock,
							 clear => clear,
							 t     => t_3,
							 q     => q3
							 );							 

t_4 <= t_3 AND q3;
							 
tff_4 : tff PORT MAP (
	                   clock => clock,
							 clear => clear,
							 t     => t_4,
							 q     => q_out
							 );							 
END rtl_ckt;