VHDL code for SR flip-flop built with NOR gates

[shaiko]

Hello,
I know this is a simple 2-1 mux :
A <= '0' when X = '1' else '1'

But what does the following generate ?
A <= '0' when X = '1' else '1' when Y = '1' ;

How can you rewrite it ?

 

[std_match]

Re: unfamiliar VHDL code

It is an SR flip-flop built with NOR gates.

X = Reset
Y = Set
A = Q


It is also called "SR latch" or "RS flip-flop" and similar.

Flip-flop (electronics) - Wikipedia, the free encyclopedia

 

[Sink0]

Re: unfamiliar VHDL code

I am not a VHDL expert (i am much more used to Verilog) but i belive that some states are missing, so it got undefined behavior.

So what happens when Y and X are 0? Undefined... it should be defined;

I belive the right should be:

A <= '0' WHEN X = '1' ELSE,
       '1' WHEN Y = '1' ELSE,
       <SOMETHING>;

Cya

 

[K-J]

Re: unfamiliar VHDL code

I am not a VHDL expert (i am much more used to Verilog) but i belive that some states are missing, so it got undefined behavior.

So what happens when Y and X are 0? Undefined... it should be defined;

I belive the right should be:

A <= '0' WHEN X = '1' ELSE,
       '1' WHEN Y = '1' ELSE,
       <SOMETHING>;

Cya

It is defined behavior, the definition being from the LRM. If there is no update for a signal then it simply maintains the current state. Which is why std_match properly classified it as an SR latch (with reset taking precedence). If neither X or Y (analogous to R and S) are set, then the output A retains its present state, whatever that is.

I suspect the behavior is the same for Verilog and is also part of the Verilog LRM.

Kevin Jennings

 

[Sink0]

Re: unfamiliar VHDL code

Yea thats is right sorry, my mistake.

 

[shaiko]

Re: unfamiliar VHDL code

K-J, std_match

You're saying that it's a transparent SR latch ?

---------- Post added at 22:00 ---------- Previous post was at 21:58 ----------

I was surprised to see pass the parsing check.
Most latches/FFs I've seen are described in a process.

 

[K-J]

Re: unfamiliar VHDL code

K-J, std_match
You're saying that it's a transparent SR latch ?

It's an SR latch...a transparent latch generally refers to a latch where you have a latch enable rather than a clock. I'm not sure what you mean by transparent SR latch, but I'm guessing that you mean it to be a latch that doesn't have an edge triggered storage. On that assumption, the original code that was posted was...

A <= '0' when X = '1' else '1' when Y = '1'

This form must be a concurrent statement, therefore it is not inside any process therefore it must be describing an SR latch not any edge triggered storage.

I was surprised to see pass the parsing check.
Most latches/FFs I've seen are described in a process.

I'm not sure what parsing check you're referring to. There is nothing invalid about the code so there is no reason why it won't make it through any compiler. However, whether you should or should not use such a thing in a design is a completely different question (hint: inside an FPGA or CPLD the answer is almost always a solid 'no'). In an ASIC, or other device where maybe there is an SR latch primitive the answer can be 'yes'.

Kevin Jennings

 

[shaiko]

Re: unfamiliar VHDL code

I've seen this code in an asychronous CPLD design...

 

[std_match]

Re: unfamiliar VHDL code

You're saying that it's a transparent SR latch ?

I was surprised to see pass the parsing check.
Most latches/FFs I've seen are described in a process.

There is no such thing as a "transparent SR latch".
"transparent latch" and "SR latch" are different, but both have combinatorial feedback.
An "SR latch" can be implemented with a D-flip-flop if you only use the "set" and "clear" inputs.
You can not implement a "transparent latch" with a D-flip-flop.

Outside of the declared processes, each assignment is it's own process.

 

[TrickyDicky]

Re: unfamiliar VHDL code

Outside of the declared processes, each assignment is it's own process.

With an infered sensitivity list.