vhdl code for pipo shifter with decrementer can anyone correct my progran plsssss

[sushma67]

i dnt know how to do looping in vhdl help me.......... code for exponent determinant using piposhiftr and decrementer
00100101 is given as i/p to pipo shifter max power of msb is 7 is given as i/p to the decrementer first 0 is shifted it should decerment to 6 secnd bit also 0 so again it should dec if 1 comes it should stp dec and shifting and tho o/p is 5
please see the block diagram below.............
untill 1 comes the loop should continue.....
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity pipo is
port(
clk : in STD_LOGIC;
pr,cr: in std_logic;
d : in STD_LOGIC_VECTOR(3 downto 0);
q : out STD_LOGIC_VECTOR(3 downto 0);s: in out std_logic_vector(3 downto 0));

end pipo;

architecture pipo of pipo is
begin
process( d,clk)
BEGIN
t:=s;
while(d(0)!='1')
if(pr='1' and cr='1' and clk='0' and clk'event)then
q(0)<=d(0);
q(1)<=d(1);
q(2)<=d(2);
q(3)<= d(3);
elsif(pr='1' and cr='0')then
q(0)<='0';
q(1)<='0';
q(2)<='0';
q(3)<= '0';
elsif(pr='0' and cr='1')then
q(0)<='1';
q(1)<='1';
q(2)<='1';
q(3)='1;'
elsif(pr='0' and cr='0')then
q(0)<='X';
q(1)<='X';
q(2)<='X';
q(3)<= 'X';

t:=t+"1111";
end if;
end loop;
s<=t;
end process;
end pipo;

 

[TrickyDicky]

Please be more clear with you question and posted code. The bottom part of the code cannot be compiled, so I suspect it is another code snippet

Please use the code forum tags!

 

[sushma67]

i kept a block diagram .... now can u correct this..... like a for loop in ac program how to do this in vhdl..can u help me plssssssssss

 

[mrflibble]

Sorry, I'm all puzzled out for today. To me it is not clear what your problem is. Maybe someone else gets it. Orrrr, if you want to be proactive about getting a solution to your problem, you could consider re-reading your own post and seeing if you can think of a way to write the problem in a clearer way. This will no doubt get you a good answer a lot faster.

Also, if you have a testbench for it (of course you have!) then could you include that as well, and a screenshot of the simulation? Again, that will get you an answer faster!

 

[sushma67]

now can u correct this.... block diagram also there and i added few changes plssssss help me

 

[TrickyDicky]

you still havent said what the problem is,

 

[mrflibble]

you still havent said what the problem is,

Yay! It wasn't just me....

[x] opinion validated.

sushma67, like TrickyDicky I don't quite understand the problem. And yes I read the entire thread and viewed the block diagram.

Do you maybe have a testbench + screenshot of this testbench where we can see what the problem is?