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VHDL code for LCD display

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j hemangini

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lcd display for xc3s700a

I am using spartan-3a starter kit & trying to write VHDL code for LCD display(2*16 character). But i am not getting success to write proper code. Could someone provide me proper code for displaying only "hello world" on display.
Thank you.
 

echo47

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xc3s700a-4 fg484

Maybe my old Verilog example will help you. Sorry it's not VHDL. It's simple crude demo code, not optimized.
I modified it to run on the Xilinx/Digilent Spartan-3A Starter Kit, part xc3s700a-4-fg484.

Code:
module top (clk, lcd_rs, lcd_rw, lcd_e, lcd_0, lcd_1, lcd_2, lcd_3, lcd_4, lcd_5, lcd_6, lcd_7);
                    parameter       k = 18;
  (* LOC="E12" *)   input           clk;        // synthesis attribute PERIOD clk "50 MHz"
                    reg   [k+8-1:0] count=0;
                    reg             lcd_busy=1;
                    reg             lcd_stb;
                    reg       [5:0] lcd_code;
                    reg       [6:0] lcd_stuff;
  (* LOC="Y14" *)   output reg      lcd_rs;
  (* LOC="W13" *)   output reg      lcd_rw;
  (* LOC="Y15" *)   output reg      lcd_7;
  (* LOC="AB16" *)  output reg      lcd_6;
  (* LOC="Y16" *)   output reg      lcd_5;
  (* LOC="AA12" *)  output reg      lcd_4;
  (* LOC="AB12" *)  output reg      lcd_3;
  (* LOC="AB17" *)  output reg      lcd_2;
  (* LOC="AB18" *)  output reg      lcd_1;
  (* LOC="Y13" *)   output reg      lcd_0;
  (* LOC="AB4" *)   output reg      lcd_e;

  always @ (posedge clk) begin
    count  <= count + 1;
    case (count[k+7:k+2])
       0: lcd_code <= 6'h03;        // power-on initialization
       1: lcd_code <= 6'h03;
       2: lcd_code <= 6'h03;
       3: lcd_code <= 6'h02;
       4: lcd_code <= 6'h02;        // function set
       5: lcd_code <= 6'h08;
       6: lcd_code <= 6'h00;        // entry mode set
       7: lcd_code <= 6'h06;
       8: lcd_code <= 6'h00;        // display on/off control
       9: lcd_code <= 6'h0C;
      10: lcd_code <= 6'h00;        // display clear
      11: lcd_code <= 6'h01;
      12: lcd_code <= 6'h24;        // H
      13: lcd_code <= 6'h28;
      14: lcd_code <= 6'h26;        // e
      15: lcd_code <= 6'h25;
      16: lcd_code <= 6'h26;        // l
      17: lcd_code <= 6'h2C;
      18: lcd_code <= 6'h26;        // l
      19: lcd_code <= 6'h2C;
      20: lcd_code <= 6'h26;        // o
      21: lcd_code <= 6'h2F;
      22: lcd_code <= 6'h22;        //
      23: lcd_code <= 6'h20;
      24: lcd_code <= 6'h25;        // W
      25: lcd_code <= 6'h27;
      26: lcd_code <= 6'h26;        // o
      27: lcd_code <= 6'h2F;
      28: lcd_code <= 6'h27;        // r
      29: lcd_code <= 6'h22;
      30: lcd_code <= 6'h26;        // l
      31: lcd_code <= 6'h2C;
      32: lcd_code <= 6'h26;        // d
      33: lcd_code <= 6'h24;
      34: lcd_code <= 6'h22;        // !
      35: lcd_code <= 6'h21;
      default: lcd_code <= 6'h10;
    endcase
//  if (lcd_rw)                     // comment-out for repeating display
//    lcd_busy <= 0;                // comment-out for repeating display
    lcd_stb <= ^count[k+1:k+0] & ~lcd_rw & lcd_busy;  // clkrate / 2^(k+2)
    lcd_stuff <= {lcd_stb,lcd_code};
    {lcd_e,lcd_rs,lcd_rw,lcd_7,lcd_6,lcd_5,lcd_4} <= lcd_stuff;
    {lcd_3,lcd_2,lcd_1,lcd_0} <= 4'b1111;
  end
endmodule
 

khamitkar.ravikant

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lcd_0 lcd_1

will it be possible to convert VERILOG to VHDL format please let me know if somebody know
 

mehrzad321

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lcd display verilog code for spartan 3a

It is very easy to convert this simple code to VHDL format but if U are as lazy az me ;) you can search for some automatic converter by googleing it, it's a peace of cake to find a good one.
 

koruprolusatish

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Re: xc3s700a-4 fg484

iam doing project on lcd display so plz give me brief explanation about this code.actually i have to display randome numbers using lcd display.









Maybe my old Verilog example will help you. Sorry it's not VHDL. It's simple crude demo code, not optimized.
I modified it to run on the Xilinx/Digilent Spartan-3A Starter Kit, part xc3s700a-4-fg484.

Code:
module top (clk, lcd_rs, lcd_rw, lcd_e, lcd_0, lcd_1, lcd_2, lcd_3, lcd_4, lcd_5, lcd_6, lcd_7);
                    parameter       k = 18;
  (* LOC="E12" *)   input           clk;        // synthesis attribute PERIOD clk "50 MHz"
                    reg   [k+8-1:0] count=0;
                    reg             lcd_busy=1;
                    reg             lcd_stb;
                    reg       [5:0] lcd_code;
                    reg       [6:0] lcd_stuff;
  (* LOC="Y14" *)   output reg      lcd_rs;
  (* LOC="W13" *)   output reg      lcd_rw;
  (* LOC="Y15" *)   output reg      lcd_7;
  (* LOC="AB16" *)  output reg      lcd_6;
  (* LOC="Y16" *)   output reg      lcd_5;
  (* LOC="AA12" *)  output reg      lcd_4;
  (* LOC="AB12" *)  output reg      lcd_3;
  (* LOC="AB17" *)  output reg      lcd_2;
  (* LOC="AB18" *)  output reg      lcd_1;
  (* LOC="Y13" *)   output reg      lcd_0;
  (* LOC="AB4" *)   output reg      lcd_e;

  always @ (posedge clk) begin
    count  <= count + 1;
    case (count[k+7:k+2])
       0: lcd_code <= 6'h03;        // power-on initialization
       1: lcd_code <= 6'h03;
       2: lcd_code <= 6'h03;
       3: lcd_code <= 6'h02;
       4: lcd_code <= 6'h02;        // function set
       5: lcd_code <= 6'h08;
       6: lcd_code <= 6'h00;        // entry mode set
       7: lcd_code <= 6'h06;
       8: lcd_code <= 6'h00;        // display on/off control
       9: lcd_code <= 6'h0C;
      10: lcd_code <= 6'h00;        // display clear
      11: lcd_code <= 6'h01;
      12: lcd_code <= 6'h24;        // H
      13: lcd_code <= 6'h28;
      14: lcd_code <= 6'h26;        // e
      15: lcd_code <= 6'h25;
      16: lcd_code <= 6'h26;        // l
      17: lcd_code <= 6'h2C;
      18: lcd_code <= 6'h26;        // l
      19: lcd_code <= 6'h2C;
      20: lcd_code <= 6'h26;        // o
      21: lcd_code <= 6'h2F;
      22: lcd_code <= 6'h22;        //
      23: lcd_code <= 6'h20;
      24: lcd_code <= 6'h25;        // W
      25: lcd_code <= 6'h27;
      26: lcd_code <= 6'h26;        // o
      27: lcd_code <= 6'h2F;
      28: lcd_code <= 6'h27;        // r
      29: lcd_code <= 6'h22;
      30: lcd_code <= 6'h26;        // l
      31: lcd_code <= 6'h2C;
      32: lcd_code <= 6'h26;        // d
      33: lcd_code <= 6'h24;
      34: lcd_code <= 6'h22;        // !
      35: lcd_code <= 6'h21;
      default: lcd_code <= 6'h10;
    endcase
//  if (lcd_rw)                     // comment-out for repeating display
//    lcd_busy <= 0;                // comment-out for repeating display
    lcd_stb <= ^count[k+1:k+0] & ~lcd_rw & lcd_busy;  // clkrate / 2^(k+2)
    lcd_stuff <= {lcd_stb,lcd_code};
    {lcd_e,lcd_rs,lcd_rw,lcd_7,lcd_6,lcd_5,lcd_4} <= lcd_stuff;
    {lcd_3,lcd_2,lcd_1,lcd_0} <= 4'b1111;
  end
endmodule


---------- Post added at 23:32 ---------- Previous post was at 23:28 ----------

can u give me links about vhdl code for lcd display
 

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