Oct 27, 2012 #1 K kannan2590 Member level 4 Joined Sep 1, 2012 Messages 77 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Location india Activity points 2,321 i have a sample of 28 bits in the input.i need a vhdl code which gives exactly one sample delay.
Oct 31, 2012 #2 G guitarguy12387 Member level 5 Joined Aug 6, 2011 Messages 94 Helped 23 Reputation 46 Reaction score 22 Trophy points 1,288 Activity points 1,743 process (<clock>) begin if rising_edge(<clock>) then <output> <= <input>; end if; end process;