vhdl code for 1 bit full adder

[mohan_ece]

vhdl code forfull adder

Hi
can anybody give the idea for desining a 1-bit full adder of behavioral modeelling using case/if ststements

 

[vyshnavi]

Re: vhdl code forfull adder

library ieee;
use ieee.std_logic-1164.all;
entity full adder is
port (
a,b,c : in std_ logic;
fsum,fcarry : out std_logic
);
end full adder;
ar... full of fulladder is
begin