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vhdl code and Xilinx SRAM-based FPGA

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lahrach

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hi friends,

----------------------------------- the example------------------------

memory_enable_lut: LUT4
generic map (INIT => X"8000")
port map( I0 => t_state,
I1 => instruction(13),
I2 => instruction(14),
I3 => memory_write,
O => memory_enable );
-----------------------------------------------------------------------


in this example is LUT4 is known for ISE as a component without defining it, or should I define it


regards :-D
 

alexan_e

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Check the examples in the attached link, there are examples how to use it



Alex
 
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