VHDL: clock events and concurrent statements

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KaluzaKlein

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Can concurrent statements be synchronous?
I have a when-else statement like the following and I want to make it execute at the rising edge of the clock:

sig1 <= '1' when (sig2 = '1') else
'0'

can it be done without a process?
 

No, it can't. Concurrent statement can only produce latch, not a flip-flop.
 
Actually they can. You have to have 1 signal creating the async logic, and another signal to register it. You can do the following to produce a flip flip:

d <= '1' when (sig2 = '1') else '0';
q <= d when rising_edge(clk); --creates a register.
 
TrickyDicky said:
Actually they can. You have to have 1 signal creating the async logic, and another signal to register it. You can do the following to produce a flip flip:

d <= '1' when (sig2 = '1') else '0';
q <= d when rising_edge(clk); --creates a register.
Click to expand...
Wow, this is so simple! I thought it won't synthesise, didn't even try...
 

Its fine for very simple things like my small example, but it can quickly get a bit unreadable. Best stick to processes and well written code.
 

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