VHDL clock divider warning

I want to divide the clock by 3 with 50% duty cycle (see below for my code). The code is synthesized successfully but when running implement design (in Xilinx ISE) I am getting following warning. I think I cannot ignore these warnings. I am a newbie to VHDL. Can anyone please tell me what changes do I need to make in my code to avoid these warning?


WARNINGhysDesignRules:372 - Gated clock. Clock net clk_div_OBUF is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:Route:455 - CLK Net:clk_div_OBUF may have excessive skew because



code:

process (clk, rst)
begin
if (rst = '0') then
pos_cnt <= (others=>'0');
elsif (rising_edge(clk)) then
if (pos_cnt = "10") then
pos_cnt <= (others => '0');
else
pos_cnt <= pos_cnt + '1';
end if;
end if;
end process;

process (clk, rst)
begin
if (rst = '0') then
neg_cnt <= (others=>'0');
elsif (falling_edge(clk)) then
if (neg_cnt = "10") then
neg_cnt <= (others => '0');
else
neg_cnt <= neg_cnt + '1';
end if;
end if;
end process;

clk_div <= '1' when ((pos_cnt /= "10") and (neg_cnt /= "10")) else
'0';

Your problem is the statement:

clk_div <= '1' when ((pos_cnt /= "10") and (neg_cnt /= "10")) else

I assume you are using clk_div as a clock input elsewhere in your design. This signal can have glitches on it (since the elements of pos_cnt don't change at EXACTLY the same time). A better way to get your desired clock might be to use a DLL or PLL.