VHDL Beginner Coding Question

[trax]

Hi, this is my first time posting. So I'm not sure if this is the right forumn section to post in. If not please redirect me to the correct one. Thanks.

I'm working on a basic game project. But I'm having worrys about synthesizing the program onto the Altera Cyclone II board.

So I basically I want to reduce some redundancy in the coding. In particular I have this for example,

This checks for one variable for multiple conditions. Is there an efficient way to extend the IF statements to check a second variable without going through the condition statements again?



if ( (DrawX = row1) and (DrawY = col2)) then --row1 2 points
G_state <= s1;
exit;
elsif ( (DrawX = row1) and (DrawY = col7)) then
G_state <= s2;
exit;
elsif ( (DrawX = row2) and (DrawY = col1)) then --row2 8 points
G_state <= s3;
exit;
elsif ( (DrawX = row2) and (DrawY = col2)) then
G_state <= s4;
exit;
.
.
.
end if;

if ( (DrawX2 = row1) and (DrawY2 = col2)) then --row1 2 points
G2_state <= s1;
exit;
elsif ( (DrawX2 = row1) and (DrawY2 = col7)) then
G2_state <= s2;
exit;
elsif ( (DrawX2 = row2) and (DrawY2 = col1)) then --row2 8 points
G2_state <= s3;
exit;
elsif ( (DrawX2 = row2) and (DrawY2 = col2)) then
G2_state <= s4;
exit;
.
.
.
end if;

What I mean is, how can I go about exchanging the variables DrawX, DrawY, G_state to their second counter parts, DrawX2, DrawY2, G2_state? Without having to go through the entire IF Condition statements again.

I was thinking along of along the lines of creating 3 dummy variables, and using a loop to go through the steps again but with an exchanged dummy variable. Would this method work? Would it reduce the resources used?

thanks for any help

 

[guitarguy12387]

Resources won't get reduced, but that might work. In HDL, loops just make the code easier to read... they get unrolled as separate circuits in hardware.

Not sure why you're using exit statements, though. I'm not sure if that's synthesizable... but maybe someone else can comment on that.

 

[TrickyDicky]

This sounds suspiciously like you think VHDL is software.
Before you write any code, think about the circuit. draw out the circuit fitst (on paper or similar), and then write the VHDL.

 

[permute]

it sounds like you want something along the lines of a procedure (or function or entity) that has inputs x,y and output s.

 

[trax]

Thanks for the replies. But I didn't want to compact the readability of the code. I was just wondering possible ways to reduce resources. Isn't calling procedures is the same as synthesizing a circuit each time as well?

 

[TrickyDicky]

Looking at your code again, I notice you have "exit" at the end of every if branch, which suggests to me these are inside a loop. You realise that loops expand into parrallel hardware right? the biggest thing to reduce hardware useage is to not use loops where you dont need them. You will always need if/elsif etc to build the mux structures required.

How about posting more of your code?

 

[permute]

you can reduce resources if you don't need both values computed each cycle.

and yes, the use of a procedure/module/function would generate as many resources as duplicating the code manually.