VHDL basic assignment question

[alexz]

Is this a legal expression?

IOLatchIn(7 downto 0)(15 downto 8) <= (others => 'Z'), latchedInputs ;

 

[Iouri]

what exactly do you want to do?

 

[alexz]

I think it is obvious from the line isn't it?
I want to concatenate 2 buses into 1

 

[keano]

signal a : std_logic_vector(7 downto 0);
signal b : std_logic_vector(4 downto 0);
signal c : std_logic_vector(2 downto 0);

a <= b & c;