Feb 5, 2007 #1 A alexz Full Member level 5 Joined Nov 19, 2004 Messages 283 Helped 6 Reputation 12 Reaction score 3 Trophy points 1,298 Location UK Activity points 2,246 Is this a legal expression? IOLatchIn(7 downto 0)(15 downto 8) <= (others => 'Z'), latchedInputs ;
Feb 5, 2007 #2 I Iouri Advanced Member level 2 Joined Aug 17, 2005 Messages 678 Helped 87 Reputation 174 Reaction score 8 Trophy points 1,298 Activity points 4,814 what exactly do you want to do?
Feb 5, 2007 #3 A alexz Full Member level 5 Joined Nov 19, 2004 Messages 283 Helped 6 Reputation 12 Reaction score 3 Trophy points 1,298 Location UK Activity points 2,246 I think it is obvious from the line isn't it? I want to concatenate 2 buses into 1
Feb 5, 2007 #4 K keano Member level 1 Joined Dec 24, 2004 Messages 36 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Location TUNISIA Activity points 251 signal a : std_logic_vector(7 downto 0); signal b : std_logic_vector(4 downto 0); signal c : std_logic_vector(2 downto 0); a <= b & c;
signal a : std_logic_vector(7 downto 0); signal b : std_logic_vector(4 downto 0); signal c : std_logic_vector(2 downto 0); a <= b & c;