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VHDL attribute enum_encoding in INCISIVE

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digitalo

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Hi all,

I'm using attribute enum_encoding to define my own encoding for enums in VHDL. However, I cannot get this annotation to work in INCISIVE (15.2). Checking the doc, the only mentions of the attribute I can find are
  • In the "VHDL Modeling Style Guide for Formal Analysis" ("Currently, only user-defined attribute ENUM_ENCODING is supported.")
  • in the description of the IGNENC error message (multiple encodings for one type).

So the documentation explicitely states that it is supported and that the use is checked. However, I can neither see any effect of adding the declaration, nor trigger the error by simulating the very example code near the error message description.

I would expect to be able to use to_unsigned(myenum'pos(state), 4) to see my encoding. However, I always see the default 0, 1, … encoding.

Is there any setting I have to use to enable enum_encoding in INCISIVE?

GENUS seems to adhere to the setting, but of course this is of little without the possibility to simulate beforehand. (I haven't yet checked the synthesis result, but I do get errors when I put invalid encodings.)

digitalo
 

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