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VHDL asynchronous event detection

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shaiko

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This is my asynchronous code for a signal rise/fall detector.
The problem is obvious - the change signal will be as short as the combinatorial delay of the transperant latch + comparator.
Any suggestions about how to make the "change" signal wider ?

------------------------------------------------------------------------
entity change_detector is
port
(
rst ,
input : in std_logic
change : out std_logic
) ;
end entity;

architecture rtl_change_detector of change_detector is

signal latched_input : std_logic ;

begin

change <= '1' when latched_input /= input else '0' ;

process ( change , rst ) is
begin
if rst = '1' then
latched_input <= '0' ;
elsif change = '1' then
latched_input <= input ;
end if ;
end process ;

end architecture rtl_change_detector ;
------------------------------------------------------------------------
 

there is something wrong with your code. pls review.
You can't read output port change.

With respect to your question: I believe FvM has put some code in another threat in the forum about this problem.

I used below code recently to deal with asynchronous rising edge:
Code:
   p_DE_FSM : process (pi_SystemClk, pi_aRst )
   begin
      if pi_aRst  = c_RstActive then
         EdgeState <= e_Zero;
      elsif rising_edge (pi_SystemClk) then
         EdgeState <= NextState;
      end if;
   end process p_DE_FSM;
      
   p_DE_StateMachine : process (EdgeState, pi_InterfaceFromSerDes.Valid)
   begin
      NextState <= EdgeState;
      DataEnable <= false;
      case EdgeState is
         when e_Zero =>
            if pi_InterfaceFromSerDes.Valid = '1' then
               NextState <= e_Edge;
            end if;
               
         when e_Edge =>
            DataEnable <= true;
            if pi_InterfaceFromSerDes.Valid = '1' then
               NextState <= e_One;
            else
               NextState <= e_Zero;
            end if;
               
         when e_One  =>
            if pi_InterfaceFromSerDes.Valid = '0' then
               NextState <= e_Zero;
            end if;
      end case;
   end process p_DE_StateMachine;
 

Yes,
I know about the read output issue. Should have been defined as a buffe.
Can you point me to the post you mentioned?
 

When writing codes like above, you should consider a simple rule
sensitivity lists are ignored in synthesis

A reasonable asynchronous change detection can be basically created by an expression

event = input xor delayed_input

For delayed_input, logic cell chains or external RC delays can be considered. The achievable delay depends on the device family and will be strongly affected by process, voltage and temperature (PVT) variations, so it canbe only roughly defined.
 

FvM,

What's the best way to create asynchronous delays inside the FPGA/CPLD ?
What do you mean in : "logic cell chains" ?
 

What do you mean in : "logic cell chains" ?
It simply means to chain a number of logic cells. The available coding methods depend on the synthesis tool. Generally you need to prevent the compiler from removing redundant logic cells, e.g. by vendor specific synthesis attributes. An example that works for Altera FPGAs is shown below, with Altera CPLDs, additional global synthesis settings are required.

Code:
library ieee;
use ieee.std_logic_1164.all;

entity chain is
  port 
  (
    inp : in  std_logic;
    outp: out std_logic
  );
end entity;

architecture rtl of chain is
signal wire1: std_logic;
signal wire2: std_logic;
signal wire3: std_logic;
signal wire4: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of wire1: signal is true;
attribute syn_keep of wire2: signal is true;
attribute syn_keep of wire3: signal is true;
attribute syn_keep of wire4: signal is true;

begin
  wire1 <= inp;
  wire2 <= wire1;
  wire3 <= wire2;
  wire4 <= wire3;
  outp <= wire4 xor inp;
end;
 

But...a wire is just a wire. It's delayed only by the wire length.
From what I see, no logic will be generated - please elaborate.
 
Last edited:

With Actel FPGAs you can instantiate delay buffers from the tech library (BUFD and INVD) that are note removed by the layout tool.
I guess Altera/Xilinx probably have got something like that.
 

But...a wire is just a wire. It's delayed only by the wire length.
From what I see, no logic will be generated - please elaborate.
What do you see. Just a few lines of code. You have to think of hardware.

These are VHDL signals, wire is just a name. Signals are usually represented by logic cells of the respective logic family, either registers or combinational ones. But you need special synthesis attributes to keep the logic cell during design optimization.

Other design tools possibly require the instantiation of logic cell primitives, or special library elements, as reported for Actel.

Simply believe that it works in Altera Quartus (with around 0.3 to 0.4 ns delay for each logic cell).

You need to find out the required syntax with your synthesis tool.
 
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