VHDL association list error sld

[Reissner]

Hi all, i am really new to vhdl.

This is my second file:

---

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_syn_attributes.all;
 
entity shiftDrAdder is
    port
    (
-- {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!
        key : in  std_logic_vector(7 downto 0);
        led : out std_logic_vector(7 downto 0)
-- {ALTERA_IO_END} DO NOT REMOVE THIS LINE!
 
    );
 
-- {ALTERA_ATTRIBUTE_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_ATTRIBUTE_END} DO NOT REMOVE THIS LINE!
end shiftDrAdder;
 
architecture ppl_type of shiftDrAdder is
  signal tdi : STD_LOGIC;
  signal tdo : STD_LOGIC;
  signal tck : STD_LOGIC;
--  signal tms : STD_LOGIC;
 
  signal cir : STD_LOGIC;
 
 
-- {ALTERA_COMPONENTS_BEGIN} DO NOT REMOVE THIS LINE!
  -- IR must have the modi
  -- 10, 01: read argument 1, 2
  --         according DR has length 2 bytes unsigned (could be 8 bits last 0)
  -- 11    : write result (suffices 8 bits to be read in at least into short) 
  -- 00    : write status (to be defined, spare) 
  component MyVJtag
    port(
      ir_out        : IN  STD_LOGIC_VECTOR (1 DOWNTO 0);
      ir_in     : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
      );
  end component;
 
-- {ALTERA_COMPONENTS_END} DO NOT REMOVE THIS LINE!
begin
-- {ALTERA_INSTANTIATION_BEGIN} DO NOT REMOVE THIS LINE!
 
 
  
  myVJtagInstance : MyVJtag port map (
    ir_out => key,
    virtual_state_cdr  => cir,--led(0),
    virtual_state_cir  => led(1),
    virtual_state_e1dr => led(2),
    virtual_state_e2dr => led(3),
    virtual_state_pdr  => led(4),
    virtual_state_sdr  => led(5),
    virtual_state_udr  => led(6),
    virtual_state_uir  => led(7),
    tdi => tdi,
    tdo => tdo,
    tck => tck
--    tms => tms,
    );
 
  led(0) <= cir;
  
-- {ALTERA_INSTANTIATION_END} DO NOT REMOVE THIS LINE!
 
end;

---

In line 64 which is

---

Code VHDL - [expand]
1
virtual_state_cdr  => cir,--led(0),

---

,
i obtain the above mentioned error.
I cannot figure out why, because i use quartus made vhdl file MyVJtag

which contains the lines

---

Code VHDL - [expand]
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ENTITY MyVJtag IS
    PORT
    (
        ir_out      : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        tdo     : IN STD_LOGIC ;
        ir_in       : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
        tck     : OUT STD_LOGIC ;
        tdi     : OUT STD_LOGIC ;
        virtual_state_cdr       : OUT STD_LOGIC ;
        virtual_state_cir       : OUT STD_LOGIC ;
        virtual_state_e1dr      : OUT STD_LOGIC ;
        virtual_state_e2dr      : OUT STD_LOGIC ;
        virtual_state_pdr       : OUT STD_LOGIC ;
        virtual_state_sdr       : OUT STD_LOGIC ;
        virtual_state_udr       : OUT STD_LOGIC ;
        virtual_state_uir       : OUT STD_LOGIC 
    );
END MyVJtag;

---

So what could be wrong with this?

 

[barry]

What's your error? It's kind of hard to figure out what those 3 fragments are. What I DO see is that your entity Myvjtag has 13 ports, but your component declaration has only 2; what's up with that?

 

[Reissner]

What's your error? It's kind of hard to figure out what those 3 fragments are. What I DO see is that your entity Myvjtag has 13 ports, but your component declaration has only 2; what's up with that?

Hi Barry,
yes, that was the deceicive hint.
Why did i make this mistake? Because i always stared at the declarations in file MyVjtag, in which the parameter occurs.
But i should have looked at the component declaration.
In C, this does not exist and so i did not realize.

Can you tell me, why in vhdl the interface of a component must be defined?
Is it to hide part of the input/output?

And THANX

greetings,

Ernst

 

[barry]

First of all, EVERYONE in the FPGA forum will yell and scream at you, so let me be the first: VHDL IS NOT SOFTWARE, IT IS FOR DEFINING HARDWARE!!! Forget about C, forget about all that other software stuff, when writing VHDL (or Verilog) you need to be fully aware of the underlying hardware. The "H' in VHDL is HARDWARE.

I don't quite understand your question, but basically, when you are instantiating components you are connecting pieces of hardware together. You can't have inputs unconnected. Nobody is trying to "hide" anything from you; on the contrary, that's why all the ports are expressly called out in the ENTITY.

 

[Reissner]

oh, so sensitive.
Well, i know that VHDL is a hardware description language and i try to configure an fpga with that.
But on the other hand, i cannot see any reason why VHDL cannot be compiled to obtain a software executable.

My second question was, why i have to declare the pins of the "enclosed" component, here MyVjtag twice:
once in the file MyVjtag where i also describe the architecture
and a second time in ShiftDrAdder where i use it.

Can you explain this to me? Why isnt is sufficient to describe the entity once
and then when i use it just cay 'component myVjtag' without again enumerating all the 'pins'?

 

[TrickyDicky]

As VHDL is for hardware description, it would make a terrible programming language, the same way C makes a terrible hardware description language. How would you convert all those parrallel processes into sequential functions?

If you dont declare the pins of your component, then they will be out of scope, and the mapper will not be able to match your component to an entity. You can compile any component you want, as you may want a black box (eg. your module is a compiled netlist rather than some other VHDL, you wouldnt bring it in until later in the compilation). So you need a component declaration that matches your entity, or it wont map. Even better, do direct instantiation, and you dont need a component at all, as it looks directly at the entity when the code is elaborated. This can save you many minutes of wasted compile time if a component could not be mapped to an entity (like I said, components are not mapped in the first pass of the code.)

Direct instantiation:

some_inst : entity my_lib.my_entity
generic map ( ...)
port map (...);

 

[barry]

Another way of looking at this: think of your component as, well, a component; an actual piece of hardware, say an IC. Just because you know what the IC pins are doesn't mean you have defined how that IC is connected to the other ICs. You may have many of those same ICs connected to other ICs. If you don't explicitly say which pins are connected to which other pins all you have is a bunch of ICs. If you draw a schematic, don't you draw wires from pin to pin? Or do you just draw some boxes and hope they somehow connect together.

 

[FvM]

Besides the already mentioned general VHDL aspect, I wonder what you want to achieve related to Altera vjtag IP.

You have generated a MyVJtag Megafunction with 8 bit virtual IR length and are combining it with some copied code that expects 2 bit IR length. You don't connect most essential JTAG signals, so the code will never cooperate with Altera JTAG tools.

A'm I right to assume that you have about no clue how the Altera VJTAG interface works or is expected to be used?

Of course, there are Altera documents explaining it (E.g. a Virtual JTAG Users Manual), but I think you should be a bit more familiar with VHDL and Altera tools before you start with this very special topic.