[VHDL] assign value to 'std_logic_vector' as decimal number (or other readable way)

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courteous

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I'd like to assign all zeros to 32-bit std_logic_vector. Is there a way to avoid writing "0000...0000"?

Probably a silly question. :smile:
 

your title and your question in the post are 2 different things.

Elexan has anwered your question in the post.

But for the question in the title - std_logic_vector is not a number, so you have to type convert via the unsigned or signed type to get a std_logic_vector. My main question is why do you want to assign a decimal number to a std_logic_vector? a std_logic_vector is just a load of bits. The signed and unsigned types are meant to be treated like integers. ANd on that note, you can do this:

my_slv <= std_logic_vector( to_unsigned( 0, my_slv'length) );

So as you can see, lots of type conversion. Avoid this by not using std_logic_vector for numbers.
 
By "decimal number" I (vaguely, I admit) implied an easy alternative to 32 zeros. Alexan_e, thank you for reminding me of others=>'0' ... I should've known this. :-|
 

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