hithesh123
Full Member level 6
I am testing a simple 'and' gate. I tried using assert when output is '1'.
But assert message pops up when simulation starts at t=0 ns and when output goes from 1 to 0.
code and waveform attached. The blue arrow tip indicates assert message was executed.
Entity ANDgate_Test is
End entity ANDgate_Test;
Library IEEE;
use IEEE.std_logic_1164.all;
Architecture test1 of Andg_Test is
Component ANDgate is
Port (A, B : in BIT;
Y: out BIT);
End component ANDgate;
signal a, b, c: BIT;
Begin
X: ANDgate port map (a, b, c);
a<= '0' after 1 NS, '1' after 10 NS, '0' after 200 NS;
b<= '0' after 1 NS, '1' after 100 NS, '0' after 300 NS;
assert c = '1'
report "Error"
severity note;
end test1;
But assert message pops up when simulation starts at t=0 ns and when output goes from 1 to 0.
code and waveform attached. The blue arrow tip indicates assert message was executed.
Entity ANDgate_Test is
End entity ANDgate_Test;
Library IEEE;
use IEEE.std_logic_1164.all;
Architecture test1 of Andg_Test is
Component ANDgate is
Port (A, B : in BIT;
Y: out BIT);
End component ANDgate;
signal a, b, c: BIT;
Begin
X: ANDgate port map (a, b, c);
a<= '0' after 1 NS, '1' after 10 NS, '0' after 200 NS;
b<= '0' after 1 NS, '1' after 100 NS, '0' after 300 NS;
assert c = '1'
report "Error"
severity note;
end test1;