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VHDL assert statement

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hithesh123

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I am testing a simple 'and' gate. I tried using assert when output is '1'.
But assert message pops up when simulation starts at t=0 ns and when output goes from 1 to 0.
code and waveform attached. The blue arrow tip indicates assert message was executed.

Entity ANDgate_Test is
End entity ANDgate_Test;


Library IEEE;
use IEEE.std_logic_1164.all;

Architecture test1 of Andg_Test is
Component ANDgate is
Port (A, B : in BIT;
Y: out BIT);
End component ANDgate;
signal a, b, c: BIT;
Begin
X: ANDgate port map (a, b, c);
a<= '0' after 1 NS, '1' after 10 NS, '0' after 200 NS;
b<= '0' after 1 NS, '1' after 100 NS, '0' after 300 NS;
assert c = '1'
report "Error"
severity note;


end test1;
 

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TrickyDicky

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whats going here is to do with the way VHDL works.
the assert statement will be checked at t=0 and then whenever c changes. Initially, c = '0' because it has not been assigned the output of the AND gate yet, because assignments like that take 1 delta cycle.

So c initially starts at '0' (because VHDL signals initialise with the leftmost value, which is '0' in the case of bit, then 1 delta cycle later it is assigned to '0' from the and gate because a and b are '0'. Then you get the assert again when the c goes from 1 to 0.

Also, I think you have slightly misunderstood how assert works, assuming you wanted output when c=1, rather than '0'. The rule is:

assert (all_is_good) report "This output occurs when allisgood is false (ie. not good)" severity NOTE;

so in your case, you probably want
assert c= '0'
 

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