signal x : 1d_array ( 0 to a - 1 ) ( b - 1 downto 0 ) ;
I want to design an array shift register that shift in a vector of '0' every clock. Something like this:
Code:
process ( clock ) is
begin
if rising_edge ( clock ) then
if load = '1' then
x <= input_array ;
else
x <= x ( 1 to a - 1 ) & ( x ( 0 ) ' range => '0' ) ;
end if ;
end if ;
end process ;
it depends what the base type is. I assume it's ambiguous as it doesnt know if ( x ( 0 ) ' range => '0' ) is a bit_vector, std_logic_vector, signed or unsigned.
use a qualification to say which one you mean:
x <= x ( 1 to a - 1 ) & std_logic_vector'( x ( 0 ) ' range => '0' ) ;
Well, the base type is already defined in the array type declaration as std_logic_vector.
Why do I need to mention it again explicitly during assignment ?
- - - Updated - - -
And also,
The apostrophe after x ( 0 ) denotes an attribute.
But what's the purpose of the apostrophe after std_logic_vector?
Code:
x <= x ( 1 to a - 1 ) & std_logic_vector [COLOR="#FF0000"]'[/COLOR] ( x ( 0 ) ' range => '0' ) ;
Well, the base type is already defined in the array type declaration as std_logic_vector.
Why do I need to mention it again explicitly during assignment ?
The compiler doesnt know that. It just knows that you made an array the length of x(0) containing '0'. That could be an array of bits, a string, an unsigned etc. It doesnt know which one you wanted to create.
- - - Updated - - -
And also,
The apostrophe after x ( 0 ) denotes an attribute.
But what's the purpose of the apostrophe after std_logic_vector?
Code:
x <= x ( 1 to a - 1 ) & std_logic_vector [COLOR="#FF0000"]'[/COLOR] ( x ( 0 ) ' range => '0' ) ;