X=> ( others => Y ) ;
X is an input port to an entity. It's defined as a custom type of an unsigned vector array.
Y is a signal defined as an unsigned vector.
When doing port map assignments - is it legal to write:
?Code:X=> ( others => Y ) ;
I see what you mean by it compiling, saying there is an error but not pointing to anything. For me, it pointed to the last line in the file. What I found is...The files are attached.
The forum doesn't allow *.vhd files, so I changed the extension to *.txt.
The error occurs when I try to compile the file named: "fifo".
controller_write_fifo_to_fifo : controller_write_fifo
controller_write_fifo_to_fifo : entity work.controller_write_fifo
Hello,
There is major upgrade to our code extraction going on that mostly a full release on 15.0. We plan to fix this crash in this new extractor but it is targeted on new family “arria 10”. We do not have plan to fix the nested generate statement related issue on older family like cyclone IV.
Thanks.
Best Regards,
Choon Hee
Actually, the problem I found is that it is limited to if you instantiate something within an 'elsif generate' like you are doing. I ran into this bug and reported it a couple of months ago. The fact that you ran across the same thing and reported it means there are at least two people reporting the same error.Kevin,
The only problem I had was with the "fifo" file.
BTW:
This design fails also fails Quartus synthesis with a crush.
I contacted Altera and opened a ticket.
I was told is that the failure was due to the use of VHDL 2008 nested "if generate".
Unless your complaint is that here it is 2014 and 2008 features are still not quite working, it would seem kind of harsh to say that they have very poor 2008 support just because you ran across a bug. Some of the things that I've seen and use from 2008 are:Apparently Quartus (14.0) has very poor 2008 support...
I've found Altera tools to be much better than Xilinx tools to the point that I basically don't bother with X anymore.All that's needed is a big enough customer that will make the jump to xilinx unless this feature is added. But you can guess how often that's happened.
Did you open a ticket with Modelsim? They didn't compile the original files either.And I doubt that they'll ever have dependable 2008 compatibility.
This is the response I got from Altera:
Yes, this is exactly my complaint...but it isn't limited to Altera.Unless your complaint is that here it is 2014 and 2008 features are still not quite working
Not yet. Will do.Did you open a ticket with Modelsim? They didn't compile the original files either.
I've found Altera tools to be much better than Xilinx tools to the point that I basically don't bother with X anymore.
Kevin Jennings
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